Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method for optimizing power in a very large scale integration (VLSI) design by detecting clock gating opportunities

Method for optimizing power in a very large scale integration (VLSI) design by detecting clock gating opportunities

US Patent 7509606 · Granted Mar 24, 2009

Estimated economic value: $7,908,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Method and apparatus for supplying power to VLSI silicon chips2025
Method and apparatus for supplying power to VLSI silicon chips2021
Reducing error rates with alpha particle protection2021
Semiconductor device with backside inductor using through silicon vias2021
On-die capacitor for a VLSI chip with backside metal plates2020
Electronic circuit having serial latch scan chains2019
Voltage droop control2018
Voltage droop control2017
Supply voltage node coupling using a switch2017
Passgate strength calibration techniques for voltage regulators2017
Dynamic adjustment of operational parameters to compensate for sensor based meas2016
Dynamic adjustment of operational parameters to compensate for sensor based meas2016