Issued Patents All Time
Showing 25 most recent of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7958311 | Cache line replacement techniques allowing choice of LFU or MFU cache line replacement | Jaime Moreno, Malcolm S. Ware | 2011-06-07 |
| 7870341 | Cache line replacement techniques allowing choice of LFU or MFU cache line replacement | Jaime Moreno, Malcolm S. Ware | 2011-01-11 |
| 7821858 | eDRAM hierarchical differential sense AMP | Stanley E. Schuster | 2010-10-26 |
| 7709299 | Hierarchical 2T-DRAM with self-timed sensing | Stanley E. Schuster | 2010-05-04 |
| 7499312 | Fast, stable, SRAM cell using seven devices and hierarchical bit/sense line | Stanley E. Schuster | 2009-03-03 |
| 7471546 | Hierarchical six-transistor SRAM | Stanley E. Schuster | 2008-12-30 |
| 7460387 | eDRAM hierarchical differential sense amp | Stanley E. Schuster | 2008-12-02 |
| 7460423 | Hierarchical 2T-DRAM with self-timed sensing | Stanley E. Schuster | 2008-12-02 |
| 7398357 | Cache line replacement techniques allowing choice of LFU or MFU cache line replacement | Jaime Moreno, Malcolm S. Ware | 2008-07-08 |
| 7289369 | DRAM hierarchical data path | Stanley E. Schuster | 2007-10-30 |
| 7133971 | Cache with selective least frequently used or most frequently used cache line replacement | Jaime Moreno, Malcolm S. Ware | 2006-11-07 |
| 6981096 | Mapping and logic for combining L1 and L2 directories and/or arrays | Stanley E. Schuster | 2005-12-27 |
| 6081872 | Cache reloading performance improvement through the use of early select techniques with and without pipelining | Stanley E. Schuster | 2000-06-27 |
| 5895487 | Integrated processing and L2 DRAM cache | William T. Boyd, Thomas J. Heller, Jr., Michael Ignatowski, Stanley E. Schuster | 1999-04-20 |
| 5890215 | Electronic computer memory system having multiple width, high speed communication buffer | Stanley E. Schuster | 1999-03-30 |
| 5870108 | Information handling system including mapping of graphics display data to a video buffer for fast updation of graphic primitives | Inching Chen | 1999-02-09 |
| 5388072 | Bit line switch array for electronic computer memory | Stanley E. Schuster | 1995-02-07 |
| 4905188 | Functional cache memory chip architecture for improved cache access | Chiao-Mei Chuang, Fred Tze-Keung Tong | 1990-02-27 |
| 4667305 | Circuits for accessing a variable width data bus with a variable width data field | Frederick Dill, Daniel T. Ling, Dennis McBride | 1987-05-19 |
| 4663729 | Display architecture having variable data width | Daniel T. Ling, Frederick Dill | 1987-05-05 |
| 4649516 | Dynamic row buffer circuit for DRAM | Paul W. Chung, Daniel T. Ling | 1987-03-10 |
| 4616310 | Communicating random access memory | Frederick Dill, Daniel T. Ling, Dennis McBride | 1986-10-07 |
| 4589092 | Data buffer having separate lock bit storage array | — | 1986-05-13 |
| 4577293 | Distributed, on-chip cache | Daniel T. Ling | 1986-03-18 |
| 4541075 | Random access memory having a second input/output port | Frederick Dill, Daniel T. Ling | 1985-09-10 |