Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7206925 | Backing Register File for processors | Quinn A. Jacobson | 2007-04-17 |
| 6757807 | Explicitly clustered register file and execution unit architecture | Quinn A. Jacobson | 2004-06-29 |
| 6356918 | Method and system for managing registers in a data processing system supports out-of-order and speculative instruction execution | Hung Q. Le | 2002-03-12 |
| 6185674 | Method and apparatus for reconstructing the address of the next instruction to be completed in a pipelined processor | Kin Shing Chan, Alessandro Marchioro | 2001-02-06 |
| 5812811 | Executing speculative parallel instructions threads with forking and inter-thread communication | Pradeep Kumar Dubey, Charles Barton, Linh H. Lam, John Kevin Patrick O'Brien, Kathryn M. O'Brien | 1998-09-22 |
| 5777918 | Fast multiple operands adder/subtracter based on shifting | Kin Shing Chan, Sang Hoo Dhong, Alessandro Marchioro | 1998-07-07 |
| 5371864 | Apparatus for concurrent multiple instruction decode in variable length instruction set computer | — | 1994-12-06 |
| 5367648 | General purpose memory access scheme using register-indirect mode | Kemal Ebciogulu | 1994-11-22 |
| 4905188 | Functional cache memory chip architecture for improved cache access | Richard E. Matick, Fred Tze-Keung Tong | 1990-02-27 |
| 4766566 | Performance enhancement scheme for a RISC type VLSI processor using dual execution units for parallel instruction processing | — | 1988-08-23 |