| 6567337 |
Pulsed circuit topology to perform a memory array write operation |
David K. Li, Robert J. Murray |
2003-05-20 |
| 6542006 |
Reset first latching mechanism for pulsed circuit topologies |
Robert J. Murray |
2003-04-01 |
| 6531897 |
Global clock self-timed circuit with self-terminating precharge for high frequency applications |
Mark S. Milshtein, Terry I. Chappell, Thomas D. Fletcher |
2003-03-11 |
| 6496038 |
Pulsed circuit topology including a pulsed, domino flip-flop |
Rajesh Kumar, Robert J. Murray |
2002-12-17 |
| 6239621 |
Two legged reset controller for domino circuit |
Mark S. Milshtein |
2001-05-29 |
| 6204714 |
Variable width pulse generator |
Mark S. Milshtein, Thomas D. Fletcher, Kevin Dai, Terry I. Chappell |
2001-03-20 |
| 5828234 |
Pulsed reset single phase domino logic |
— |
1998-10-27 |
| 5796282 |
Latching mechanism for pulsed domino logic with inherent race margin and time borrowing |
Robert J. Murray |
1998-08-18 |