MZ

Matthew M. Ziegler

IBM: 22 patents #4,909 of 70,183Top 7%
Overall (All Time): #193,138 of 4,157,543Top 5%
22
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
11636245 Methods and systems for leveraging computer-aided design variability in synthesis tuning Lakshmi N. Reddy, Robert L. Franch 2023-04-25
10789400 Scheduling simultaneous optimization of multiple very-large-scale-integration designs Hung-Yi Liu 2020-09-29
10296691 Optimizing the layout of circuits based on multiple design constraints Robert L. Franch, George D. Gristede 2019-05-21
10263519 Resonant virtual supply booster for synchronous digital circuits having a predictable evaluate time Rajiv V. Joshi 2019-04-16
10083268 Scheduling simultaneous optimization of multiple very-large-scale-integration designs Hung-Yi Liu 2018-09-25
10002221 Enhanced parameter tuning for very-large-scale integration synthesis Hung-Yi Liu 2018-06-19
9934344 Enhanced parameter tuning for very-large-scale integration synthesis Hung-Yi Liu 2018-04-03
9910949 Synthesis tuning system for VLSI design optimization George D. Gristede 2018-03-06
9703920 Intra-run design decision process for circuit synthesis Christopher J. Berry, Lakshmi N. Reddy, Sourav Saha 2017-07-11
9690900 Intra-run design decision process for circuit synthesis Christopher J. Berry, Lakshmi N. Reddy, Sourav Saha 2017-06-27
9660530 Resonant virtual supply booster for synchronous digital circuits having a predictable evaluate time Rajiv V. Joshi 2017-05-23
9619602 Enhanced parameter tuning for very-large-scale integration synthesis Hung-Yi Liu 2017-04-11
9600623 Scheduling simultaneous optimization of multiple very-large-scale-integration designs Hung-Yi Liu 2017-03-21
9582627 Enhanced parameter tuning for very-large-scale integration synthesis Hung-Yi Liu 2017-02-28
9529951 Synthesis tuning system for VLSI design optimization George D. Gristede 2016-12-27
8954914 Graphical method and product to assign physical attributes to entities in a high level descriptive language used for VLSI chip design John T. Badar, David W. Lewis, Michael H. Wood 2015-02-10
8839162 Specifying circuit level connectivity during circuit design synthesis Michael D. Amundson, Dorothy Kucar, Ruchir Puri, Chin Ngai Sze 2014-09-16
8756541 Relative ordering circuit synthesis Minsik Cho, Ruchir Puri, Haoxing Ren, Xiaoping Tang, Hua Xiang 2014-06-17
8566761 Network flow based datapath bit slicing Hua Xiang, Minsik Cho, Haoxing Ren, Ruchir Puri 2013-10-22
8516412 Soft hierarchy-based physical synthesis for large-scale, high-performance circuits Minsik Cho, Alvan W. Ng, Ruchir Puri, Haoxing Ren, Hua Xiang 2013-08-20
8495552 Structured latch and local-clock-buffer planning Minsik Cho, Ruchir Puri, Haoxing Ren, Hua Xiang 2013-07-23
8271920 Converged large block and structured synthesis for high performance microprocessor designs Minsik Cho, Victor N. Kravets, Smita Krishnaswamy, Dorothy Kucar, Jagannathan Narasimhan +6 more 2012-09-18