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Implementing enhanced physical design quality using historical placement analytics |
Joel R. Earl, Timothy D. Helvey, David A. Lawson, Michael T. Repede |
2015-12-29 |
| 9218445 |
Implementing enhanced physical design quality using historical placement analytics |
Joel R. Earl, Timothy D. Helvey, David A. Lawson, Michael T. Repede |
2015-12-22 |
| 8839162 |
Specifying circuit level connectivity during circuit design synthesis |
Dorothy Kucar, Ruchir Puri, Chin Ngai Sze, Matthew M. Ziegler |
2014-09-16 |
| 8683402 |
Clock alias for timing analysis of an integrated circuit design |
Craig M. Darsow |
2014-03-25 |
| 8448113 |
Efficiently applying a single timing assertion to multiple timing points in a circuit using creating a deffinition |
Craig M. Darsow |
2013-05-21 |
| 8438514 |
Clock alias for timing analysis of an integrated circuit design |
Craig M. Darsow |
2013-05-07 |
| 8296707 |
Implementing spare latch placement quality determination |
Craig M. Darsow, Eldon Nelson, Dennis Martin Rickert |
2012-10-23 |
| 8250515 |
Clock alias for timing analysis of an integrated circuit design |
Craig M. Darsow |
2012-08-21 |
| 8001496 |
Control of design automation process |
— |
2011-08-16 |
| 7895544 |
Method to graphically identify registers with unbalanced slack as part of placement driven synthesis optimization |
— |
2011-02-22 |
| 7100140 |
Generation of graphical congestion data during placement driven synthesis optimization |
Brian C. Wilson |
2006-08-29 |
