TH

Timothy D. Helvey

IBM: 18 patents #6,125 of 70,183Top 9%
Overall (All Time): #255,501 of 4,157,543Top 7%
18
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
9858380 Determining positions of storage elements in a logic design David A. Lawson 2018-01-02
9223923 Implementing enhanced physical design quality using historical placement analytics Michael D. Amundson, Joel R. Earl, David A. Lawson, Michael T. Repede 2015-12-29
9218445 Implementing enhanced physical design quality using historical placement analytics Michael D. Amundson, Joel R. Earl, David A. Lawson, Michael T. Repede 2015-12-22
9087172 Implementing enhanced net routing congestion resolution of non-rectangular or rectangular hierarchical macros Matthew R. Ellavsky, Sean T. Evans, Brandon E. Schenck, Jason L. Van Vreede, Bradley C. White 2015-07-21
8949755 Analyzing sparse wiring areas of an integrated circuit design — 2015-02-03
8826214 Implementing Z directional macro port assignment Matthew R. Ellavsky, Sean T. Evans, Phillip P. Normand, Jason L. Van Vreede, Bradley C. White 2014-09-02
8819612 Analyzing timing requirements of a hierarchical integrated circuit design — 2014-08-26
8689170 Changing the location of a buffer bay in a netlist Matthew R. Ellavsky, Sean T. Evans, Phillip P. Normand, Jason L. VanVreede, Bradley C. White 2014-04-01
8631370 Swapping ports to change the timing window overlap of adjacent nets Samuel R. Benjamin 2014-01-14
8473884 Slack-based timing budget apportionment Ronald J. Daede 2013-06-25
8448121 Implementing Z directional macro port assignment Matthew R. Ellavsky, Sean T. Evans, Phillip P. Normand, Jason L. Van Vreede, Bradley C. White 2013-05-21
8448123 Implementing net routing with enhanced correlation of pre-buffered and post-buffered routes Paul G. Curtis 2013-05-21
8413104 Changing the location of a buffer bay in a netlist Matthew R. Ellavsky, Sean T. Evans, Phillip P. Normand, Jason L. Van Vreede, Bradley C. White 2013-04-02
8316333 Implementing timing pessimism reduction for parallel clock trees Craig M. Darsow 2012-11-20
8271923 Implementing forward tracing to reduce pessimism in static timing of logic blocks laid out in parallel structures on an integrated circuit chip Craig M. Darsow 2012-09-18
8250509 Slack-based timing budget apportionment Ronald J. Daede 2012-08-21
8024683 Replicating timing data in static timing analysis operation Craig M. Darsow 2011-09-20
7962871 Concurrently modeling delays between points in static timing analysis operation Craig M. Darsow 2011-06-14