| 8826214 |
Implementing Z directional macro port assignment |
Matthew R. Ellavsky, Sean T. Evans, Timothy D. Helvey, Jason L. Van Vreede, Bradley C. White |
2014-09-02 |
| 8689170 |
Changing the location of a buffer bay in a netlist |
Matthew R. Ellavsky, Sean T. Evans, Timothy D. Helvey, Jason L. VanVreede, Bradley C. White |
2014-04-01 |
| 8448121 |
Implementing Z directional macro port assignment |
Matthew R. Ellavsky, Sean T. Evans, Timothy D. Helvey, Jason L. Van Vreede, Bradley C. White |
2013-05-21 |
| 8413104 |
Changing the location of a buffer bay in a netlist |
Matthew R. Ellavsky, Sean T. Evans, Timothy D. Helvey, Jason L. Van Vreede, Bradley C. White |
2013-04-02 |
| 8356264 |
Implementing enhanced clock tree distributions to decouple across N-level hierarchical entities |
Mark R. Lasher, Daniel R. Menard |
2013-01-15 |
| 7073145 |
Programmable delay method for hierarchical signal balancing |
Thomas W. Fry, Daniel R. Menard |
2006-07-04 |
| 6990645 |
Method for static timing verification of integrated circuits having voltage islands |
Susan K. Lichtensteiger, Timothy M. Platt |
2006-01-24 |
| 6986116 |
Signal balancing between voltage domains |
Thomas W. Fry, Daniel R. Menard |
2006-01-10 |
