| 8683402 |
Clock alias for timing analysis of an integrated circuit design |
Michael D. Amundson |
2014-03-25 |
| 8612910 |
Clock alias for timing analysis of an integrated circuit design |
Michael D. Amudson |
2013-12-17 |
| 8448113 |
Efficiently applying a single timing assertion to multiple timing points in a circuit using creating a deffinition |
Michael D. Amundson |
2013-05-21 |
| 8438514 |
Clock alias for timing analysis of an integrated circuit design |
Michael D. Amundson |
2013-05-07 |
| 8316333 |
Implementing timing pessimism reduction for parallel clock trees |
Timothy D. Helvey |
2012-11-20 |
| 8296707 |
Implementing spare latch placement quality determination |
Michael D. Amundson, Eldon Nelson, Dennis Martin Rickert |
2012-10-23 |
| 8271923 |
Implementing forward tracing to reduce pessimism in static timing of logic blocks laid out in parallel structures on an integrated circuit chip |
Timothy D. Helvey |
2012-09-18 |
| 8250515 |
Clock alias for timing analysis of an integrated circuit design |
Michael D. Amundson |
2012-08-21 |
| 8024683 |
Replicating timing data in static timing analysis operation |
Timothy D. Helvey |
2011-09-20 |
| 7962871 |
Concurrently modeling delays between points in static timing analysis operation |
Timothy D. Helvey |
2011-06-14 |
| 7636905 |
Performing static timing analysis of an integrated circuit design using dummy edge modeling |
Todd Edward Obermiller |
2009-12-22 |
| 7269812 |
Apparatus and method for performing static timing analysis of an integrated circuit design |
Todd Edward Obermiller |
2007-09-11 |
| 7143379 |
Apparatus and method for performing static timing analysis of an integrated circuit design using dummy edge modeling |
Todd Edward Obermiller |
2006-11-28 |
