| 9058456 |
Method and system to fix early mode slacks in a circuit design |
Wilhelm Haller, Ulrich Krauch, Kurt Lind |
2015-06-16 |
| 8964493 |
Defective memory column replacement with load isolation |
Silke Penth, Raphael Polig, Tobias Werner |
2015-02-24 |
| 8631376 |
Method and system for generating a placement layout of a VLSI circuit design |
Tobias Werner, Anthony Parent, Raphael Polig |
2014-01-14 |
| 8522182 |
Generation of an end point report for a timing simulation of an integrated circuit |
Ulrich Krauch, Kurt Lind |
2013-08-27 |
| 8316335 |
Multistage, hybrid synthesis processing facilitating integrated circuit layout |
Harry Barowski, Harold Mielich, Friedrich Schroeder |
2012-11-20 |
| 7557614 |
Topology for a n-way XOR/XNOR circuit |
Stefan Bonsels, Martin Padeffke, Tobias Werner |
2009-07-07 |
| 7546565 |
Method for comparing two designs of electronic circuits |
Joachim Fenkes, Wilhelm Haller, Tobias Werner |
2009-06-09 |
| 7490310 |
Method for creating a layout for an electronic circuit |
Juergen Koehl, Urich Kranch, Juerge Pilk, Helmut Zudrell |
2009-02-10 |
| 7401312 |
Automatic method for routing and designing an LSI |
Ulrich Krauch, Juergen Pille, Tobias Werner |
2008-07-15 |
| 6912473 |
Method for verifying cross-sections |
Dieter Wendel |
2005-06-28 |
