Issued Patents All Time
Showing 25 most recent of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9256430 | Instruction scheduling approach to improve processor performance | Juergen Koehl, Philipp Panitz, Hans Schlenker | 2016-02-09 |
| 9207995 | Mechanism to speed-up multithreaded execution by register file write port reallocation | Maarten J. Boersma, Markus Kaltenbach, Tim Niggemeier, Philipp Oehler, Philipp Panitz | 2015-12-08 |
| 9164725 | Apparatus and method for calculating an SHA-2 hash function in a general purpose processor | Maarten J. Boersma, Markus Kaltenbach, Tim Niggemeier, Philipp Oehler, Philipp Panitz | 2015-10-20 |
| 9043673 | Techniques for reusing components of a logical operations functional block as an error correction code correction unit | Markus Kaltenback, Philipp Oehler, Philipp Panitz | 2015-05-26 |
| 8977835 | Reversing processing order in half-pumped SIMD execution units to achieve K cycle issue-to-issue latency | Maarten J. Boersma, Markus Kaltenbach, Christophe J. Layer, Silvia M. Mueller | 2015-03-10 |
| 8972961 | Instruction scheduling approach to improve processor performance | Juergen Koehl, Philipp Panitz, Hans Schlenker | 2015-03-03 |
| 8959276 | Byte selection and steering logic for combined byte shift and byte permute vector unit | Markus Kaltenbach, Philipp Panitz, Christoph Wandel | 2015-02-17 |
| 8959275 | Byte selection and steering logic for combined byte shift and byte permute vector unit | Markus Kaltenbach, Philipp Panitz, Christoph Wandel | 2015-02-17 |
| 8949575 | Reversing processing order in half-pumped SIMD execution units to achieve K cycle issue-to-issue latency | Maarten J. Boersma, Markus Kaltenbach, Christophe J. Layer, Silvia M. Mueller | 2015-02-03 |
| 8935685 | Instruction scheduling approach to improve processor performance | Juergen Koehl, Philipp Panitz, Hans Schlenker | 2015-01-13 |
| 8903882 | Method and data processing unit for calculating at least one multiply-sum of two carry-less multiplications of two input operands, data processing program and computer program product | Maarten J. Boersma, Markus Kaltenbach, Tim Niggemeier, Philipp Oehler, Philipp Panitz | 2014-12-02 |
| 8843527 | Fast predicate table scans using single instruction, multiple data architecture | Eduard Diner, Vijayshankar Raman, Adam J. Storm | 2014-09-23 |
| 8832158 | Fast predicate table scans using single instruction, multiple data architecture | Eduard Diner, Vijayshankar Raman, Adam J. Storm | 2014-09-09 |
| 8312069 | Permute unit and method to operate a permute unit | Tobias Gemmeke, Dieter Wendel | 2012-11-13 |
| 8046566 | Method to reduce power consumption of a register file with multi SMT support | Christopher M. Abernathy, Nicolas Maeding, Dung Q. Nguyen | 2011-10-25 |
| 7962538 | Method of operand width reduction to enable usage of narrower saturation adder | Tobias Gemmeke, Nicolas Maeding, Kerstin Claudia Schelm | 2011-06-14 |
| 7913132 | System and method for scanning sequential logic elements | Tobias Gemmeke, Dieter Wendel, Holger Wetter | 2011-03-22 |
| 7890901 | Method and system for verifying the equivalence of digital circuits | Tobias Gemmeke, Nicolas Maeding, Hari Mony | 2011-02-15 |
| 7844799 | Method and system for pipeline reduction | Antje Mueller, Juergen Pille, Dieter Wendel | 2010-11-30 |
| 7783690 | Electronic circuit for implementing a permutation operation | Nicolas Maeding, Amaury Neve de Mevergnies, Hans-Werner Tast | 2010-08-24 |
| 7769986 | Method and apparatus for register renaming | Christopher M. Abernathy, William E. Burky, Nicolas Maeding | 2010-08-03 |
| 7735038 | Design structure to reduce power consumption within a clock gated synchronous circuit and clock gated synchronous circuit | Tobias Gemmeke, Jochen Preiss | 2010-06-08 |
| 7639046 | Method to reduce power consumption within a clock gated synchronous circuit and clock gated synchronous circuit | Tobias Gemmeke, Jochen Preiss | 2009-12-29 |
| 7509511 | Reducing register file leakage current within a processor | Harry Barowski, Tobias Gemmeke, Tim Niggemeier | 2009-03-24 |
| 7469332 | Systems and methods for adaptively mapping an instruction cache | Claude Basso, Jean Calvignac, Chih-jen Chang, Harm Peter Hofstee, Hans-Werner Tast +2 more | 2008-12-23 |