Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12340161 | Multi-layer integrated circuit routing tool | Ralf Richter | 2025-06-24 |
| 11354478 | Semiconductor circuit design and unit pin placement | Ralf Richter | 2022-06-07 |
| 10997350 | Semiconductor circuit design and unit pin placement | Ralf Richter | 2021-05-04 |
| 10936773 | Sink-based wire tagging in multi-sink integrated circuit net | Sven Peyer | 2021-03-02 |
| 10353841 | Optimizing routing of a signal path in a semiconductor device | — | 2019-07-16 |
| 10031996 | Timing based net constraints tagging with zero wire load validation | Florian Braun | 2018-07-24 |
| 9727687 | Method for calculating an effect on timing of moving a pin from an edge to an inboard position in processing large block synthesis (LBS) | Niels Fricke, Michael H. Wood | 2017-08-08 |
| 9418198 | Method for calculating an effect on timing of moving a pin from an edge to an inboard position in processing large block synthesis (LBS) | Niels Fricke, Michael H. Wood | 2016-08-16 |
| 8930870 | Optimized buffer placement based on timing and capacitance assertions | Elmar Gaugler, Ralf Richter | 2015-01-06 |
| 8566774 | Optimized buffer placement based on timing and capacitance assertions | Elmar Gaugler, Ralf Richter | 2013-10-22 |
| 8423940 | Early noise detection and noise aware routing in circuit design | Elmar Gaugler, Wilhelm Haller, Ralf Richter | 2013-04-16 |
| 7966597 | Method and system for routing of integrated circuit design | — | 2011-06-21 |