Issued Patents All Time
Showing 126–150 of 358 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9928173 | Conditional inclusion of data in a transactional memory read set | Michael K. Gschwind, Eric M. Schwarz, Timothy J. Slegel | 2018-03-27 |
| 9928132 | Dynamic accessing of execution elements through modification of issue rules | Fadi Y. Busaba, Steven R. Carlough, Christopher A. Krygowski, Brian R. Prasky | 2018-03-27 |
| 9928064 | Instruction stream modification for memory transaction protection | Fadi Y. Busaba, Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Timothy J. Slegel | 2018-03-27 |
| 9921965 | Demote instruction for relinquishing cache line ownership | Kathryn Marie Jackson, Charles F. Webb | 2018-03-20 |
| 9921964 | Demote instruction for relinquishing cache line ownership | Kathryn Marie Jackson, Charles F. Webb | 2018-03-20 |
| 9921895 | Transactional memory operations with read-only atomicity | Michael K. Gschwind, Eric M. Schwarz, Timothy J. Slegel | 2018-03-20 |
| 9921872 | Interprocessor memory status communication | Dan F. Greiner, Maged M. Michael, Valentina Salapura, Eric M. Schwarz, Timothy J. Slegel | 2018-03-20 |
| 9916180 | Interprocessor memory status communication | Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Eric M. Schwarz, Timothy J. Slegel | 2018-03-13 |
| 9916179 | Interprocessor memory status communication | Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Eric M. Schwarz, Timothy J. Slegel | 2018-03-13 |
| 9904572 | Dynamic prediction of hardware transaction resource requirements | Fadi Y. Busaba, Dan F. Greiner, Michael K. Gschwind, Maged M. Michael, Valentina Salapura | 2018-02-27 |
| 9898331 | Dynamic releasing of cache lines | Jonathan D. Bradbury, Michael K. Gschwind, Timothy J. Slegel | 2018-02-20 |
| 9898294 | Selectively blocking branch prediction for a predetermined number of instructions | James J. Bonanno, Ulrich Mayer, Anthony Saporito, Timothy J. Slegel | 2018-02-20 |
| 9892052 | Hybrid tracking of transaction read and write sets | Michael K. Gschwind, Valentina Salapura | 2018-02-13 |
| 9891922 | Selectively blocking branch prediction for a predetermined number of instructions | James J. Bonanno, Ulrich Mayer, Anthony Saporito, Timothy J. Slegel | 2018-02-13 |
| 9870254 | Multithreaded transactions | Fadi Y. Busaba, Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz | 2018-01-16 |
| 9864692 | Managing read tags in a transactional memory | Dan F. Greiner, Michael K. Gschwind, Eric M. Schwarz, Timothy J. Slegel | 2018-01-09 |
| 9864690 | Detecting cache conflicts by utilizing logical address comparisons in a transactional memory | Michael K. Gschwind, Eric M. Schwarz, Timothy J. Slegel | 2018-01-09 |
| 9864639 | Management of resources within a computing environment | Fadi Y. Busaba, Steven R. Carlough, Christopher A. Krygowski, Brian R. Prasky | 2018-01-09 |
| 9858074 | Non-default instruction handling within transaction | Jonathan D. Bradbury, Michael K. Gschwind, Maged M. Michael, Eric M. Schwarz, Valentina Salapura | 2018-01-02 |
| 9858189 | Hybrid tracking of transaction read and write sets | Michael K. Gschwind, Valentina Salapura | 2018-01-02 |
| 9852014 | Deferral instruction for managing transactional aborts in transactional memory computing environments | Timothy J. Slegel | 2017-12-26 |
| 9851971 | Latent modification instruction for transactional execution | Michael K. Gschwind, Valentina Salapura, Timothy J. Slegel | 2017-12-26 |
| 9846593 | Predicting the length of a transaction | Jonathan D. Bradbury, Harold W. Cain, III, Michael K. Gschwind, Maged M. Michael, Valentina Salapura +1 more | 2017-12-19 |
| 9836405 | Dynamic management of virtual memory blocks exempted from cache memory access | Jonathan D. Bradbury, Dan F. Greiner, Michael K. Gschwind, Christian Jacobi, Younes Manton +1 more | 2017-12-05 |
| 9830159 | Suspending branch prediction upon entering transactional execution mode | Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz | 2017-11-28 |