Issued Patents All Time
Showing 151–175 of 358 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9830159 | Suspending branch prediction upon entering transactional execution mode | Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz | 2017-11-28 |
| 9798545 | Anticipated prefetching for a parent core in a multi-core chip | Brian R. Prasky, Fadi Y. Busaba, Steven R. Carlough, Christopher A. Krygowski | 2017-10-24 |
| 9792120 | Anticipated prefetching for a parent core in a multi-core chip | Brian R. Prasky, Fadi Y. Busaba, Steven R. Carlough, Christopher A. Krygowski | 2017-10-17 |
| 9772944 | Transactional execution in a multi-processor environment that monitors memory conflicts in a shared cache | Fadi Y. Busaba, Michael K. Gschwind, Eric M. Schwarz | 2017-09-26 |
| 9760495 | Hybrid tracking of transaction read and write sets | Michael K. Gschwind, Valentina Salapura | 2017-09-12 |
| 9760494 | Hybrid tracking of transaction read and write sets | Michael K. Gschwind, Valentina Salapura | 2017-09-12 |
| 9760397 | Interprocessor memory status communication | Dan F. Greiner, Maged M. Michael, Valentina Salapura, Eric M. Schwarz, Timothy J. Slegel | 2017-09-12 |
| 9740616 | Multi-granular cache management in multi-processor computing environments | Fadi Y. Busaba, Harold W. Cain, III, Michael K. Gschwind, Maged M. Michael, Valentina Salapura +1 more | 2017-08-22 |
| 9740615 | Processor directly storing address range of co-processor memory accesses in a transactional memory where co-processor supplements functions of the processor | Jonathan D. Bradbury, Michael K. Gschwind, Eric M. Schwarz, Timothy J. Slegel | 2017-08-22 |
| 9740614 | Processor directly storing address range of co-processor memory accesses in a transactional memory where co-processor supplements functions of the processor | Jonathan D. Bradbury, Michael K. Gschwind, Eric M. Schwarz, Timothy J. Slegel | 2017-08-22 |
| 9727484 | Dynamic cache memory management with translation lookaside buffer protection | Jonathan D. Bradbury, Michael K. Gschwind, Christian Jacobi, Anthony Saporito, Timothy J. Slegel | 2017-08-08 |
| 9720837 | Allowing non-cacheable loads within a transaction | Jonathan D. Bradbury, Michael K. Gschwind, Valentina Salapura | 2017-08-01 |
| 9715377 | Behavior based code recompilation triggering scheme | Jonathan D. Bradbury, Giles R. Frazier, Michael K. Gschwind, Christian Jacobi, Anthony Saporito | 2017-07-25 |
| 9710271 | Collecting transactional execution characteristics during transactional execution | Fadi Y. Busaba, Harold W. Cain, III, Dan F. Greiner, Michael K. Gschwind, Valentina Salapura +1 more | 2017-07-18 |
| 9703718 | Managing read tags in a transactional memory | Dan F. Greiner, Michael K. Gschwind, Eric M. Schwarz, Timothy J. Slegel | 2017-07-11 |
| 9703560 | Collecting transactional execution characteristics during transactional execution | Fadi Y. Busaba, Harold W. Cain, III, Dan F. Greiner, Michael K. Gschwind, Valentina Salapura +1 more | 2017-07-11 |
| 9697121 | Dynamic releasing of cache lines | Jonathan D. Bradbury, Michael K. Gschwind, Timothy J. Slegel | 2017-07-04 |
| 9690623 | Regulating hardware speculative processing around a transaction | Fadi Y. Busaba, Michael K. Gschwind, Eric M. Schwarz | 2017-06-27 |
| 9690556 | Code optimization to enable and disable coalescing of memory transactions | Fadi Y. Busaba, Michael K. Gschwind, Maged M. Michael, Valentina Salapura | 2017-06-27 |
| 9684599 | Hybrid tracking of transaction read and write sets | Michael K. Gschwind, Valentina Salapura | 2017-06-20 |
| 9684537 | Regulating hardware speculative processing around a transaction | Fadi Y. Busaba, Michael K. Gschwind, Eric M. Schwarz | 2017-06-20 |
| 9658961 | Speculation control for improving transaction success rate, and instruction therefor | Michael K. Gschwind, Valentina Salapura, Eric M. Schwarz, Timothy J. Slegel | 2017-05-23 |
| 9639370 | Software instructed dynamic branch history pattern adjustment | Michael K. Gschwind, Christian Jacobi, Anthony Saporito, Timothy J. Slegel | 2017-05-02 |
| 9626189 | Reducing operand store compare penalties | Fadi Y. Busaba, David S. Hutton, John G. Rell, Jr. | 2017-04-18 |
| 9619384 | Demote instruction for relinquishing cache line ownership | Kathryn Marie Jackson, Charles F. Webb | 2017-04-11 |