Issued Patents All Time
Showing 51–75 of 112 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9626187 | Transactional memory system supporting unbroken suspended execution | Bradly G. Frey, Benjamin Herrenschmidt, Hung Q. Le, Cathy May, Maged M. Michael +4 more | 2017-04-18 |
| 9626256 | Determining failure context in hardware transactional memories | Bradly G. Frey, Hung Q. Le, Cathy May | 2017-04-18 |
| 9619345 | Apparatus for determining failure context in hardware transactional memories | Bradly G. Frey, Hung Q. Le, Cathy May | 2017-04-11 |
| 9619383 | Dynamic predictor for coalescing memory transactions | Fadi Y. Busaba, Michael K. Gschwind, Maged M. Michael, Eric M. Schwarz | 2017-04-11 |
| 9619356 | Detection of hardware errors using periodically synchronized redundant transactions and comparing results from cores of a multi-core processor | David M. Daly, Kattamuri Ekanadham, Michael C. Huang, Jose E. Moreira, Mauricio J. Serrano | 2017-04-11 |
| 9547595 | Salvaging lock elision transactions | Michael K. Gschwind, Maged M. Michael, Chung-Lung K. Shum | 2017-01-17 |
| 9535608 | Memory access request for a memory protocol | Fadi Y. Busaba, Michael K. Gschwind, Valentina Salapura, Timothy J. Slegel | 2017-01-03 |
| 9529723 | Methods of cache preloading on a partition or a context switch | Vijayalakshmi Srinivasan, Jason D. Zebchuk | 2016-12-27 |
| 9507628 | Memory access request for a memory protocol | Fadi Y. Busaba, Michael K. Gschwind, Valentina Salapura, Timothy J. Slegel | 2016-11-29 |
| 9459979 | Detection of hardware errors using redundant transactions for system test | David M. Daly, Kattamuri Ekanadham, Michael C. Huang, Jose E. Moreira, Mauricio J. Serrano | 2016-10-04 |
| 9454483 | Salvaging lock elision transactions with instructions to change execution type | Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Chung-Lung K. Shum | 2016-09-27 |
| 9448835 | Thread-based cache content saving for task switching | David M. Daly, Brian R. Prasky, Vijayalakshmi Srinivasan | 2016-09-20 |
| 9448836 | Alerting hardware transactions that are about to run out of space | Fadi Y. Busaba, Michael K. Gschwind, Maged M. Michael, Valentina Salapura | 2016-09-20 |
| 9442853 | Salvaging lock elision transactions with instructions to change execution type | Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Chung-Lung K. Shum | 2016-09-13 |
| 9442775 | Salvaging hardware transactions with instructions to transfer transaction execution control | Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Chung-Lung K. Shum | 2016-09-13 |
| 9442776 | Salvaging hardware transactions with instructions to transfer transaction execution control | Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Chung-Lung K. Shum | 2016-09-13 |
| 9436501 | Thread-based cache content saving for task switching | David M. Daly, Brian R. Prasky, Vijayalakshmi Srinivasan | 2016-09-06 |
| 9430273 | Suppressing aborting a transaction beyond a threshold execution duration based on the predicted duration | Jonathan D. Bradbury, Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Chung-Lung K. Shum +1 more | 2016-08-30 |
| 9424072 | Alerting hardware transactions that are about to run out of space | Fadi Y. Busaba, Michael K. Gschwind, Maged M. Michael, Valentina Salapura | 2016-08-23 |
| 9411729 | Salvaging lock elision transactions | Michael K. Gschwind, Maged M. Michael, Chung-Lung K. Shum | 2016-08-09 |
| 9389802 | Hint instruction for managing transactional aborts in transactional memory computing environments | Fadi Y. Busaba, Dan F. Greiner, Michael K. Gschwind, Maged M. Michael, Valentina Salapura +2 more | 2016-07-12 |
| 9361041 | Hint instruction for managing transactional aborts in transactional memory computing environments | Fadi Y. Busaba, Dan F. Greiner, Michael K. Gschwind, Maged M. Michael, Valentina Salapura +2 more | 2016-06-07 |
| 9342397 | Salvaging hardware transactions with instructions | Fadi Y. Busaba, Maged M. Michael, Valentina Salapura, Eric M. Schwarz | 2016-05-17 |
| 9336097 | Salvaging hardware transactions | Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Eric M. Schwarz | 2016-05-10 |
| 9329890 | Managing high-coherence-miss cache lines in multi-processor computing environments | Fadi Y. Busaba, Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Eric M. Schwarz +1 more | 2016-05-03 |