Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10725782 | Providing variable interpretation of usefulness indicators for memory tables in processor-based systems | Yongseok Yi, Eric Rotenberg, Vignyan Reddy Kothinti Naresh, Gregory M. Wright | 2020-07-28 |
| 10635446 | Reconfiguring execution pipelines of out-of-order (OOO) computer processors based on phase training and prediction | Shivam Priyadarshi, Raguram Damodaran | 2020-04-28 |
| 10551896 | Method and apparatus for dynamic clock and voltage scaling in a computer processor based on program phase | Shivam Priyadarshi, Raguram Damodaran, Jeffrey Todd Bridges, Ryan D. Wells, Norman S. Gargash +1 more | 2020-02-04 |
| 10437592 | Reduced logic level operation folding of context history in a history register in a prediction system for a processor-based system | Yongseok Yi, Vignyan Reddy Kothinti Naresh | 2019-10-08 |
| 10331447 | Providing efficient recursion handling using compressed return address stacks (CRASs) in processor-based systems | Vignyan Reddy Kothinti Naresh | 2019-06-25 |
| 10108417 | Storing narrow produced values for instruction operands directly in a register map in an out-of-order processor | Rodney Wayne Smith, Sandeep Suresh Navada, Shivam Priyadarshi, Raguram Damodaran | 2018-10-23 |
| 9851774 | Method and apparatus for dynamic clock and voltage scaling in a computer processor based on program phase | Shivam Priyadarshi, Raguram Damodaran, Jeffrey Todd Bridges, Ryan D. Wells, Norman S. Gargash +1 more | 2017-12-26 |
| 9471325 | Method and apparatus for selective renaming in a microprocessor | Sandeep Suresh Navada, Niket K. Choudhary, Michael Scott McIlvaine, Thomas Andrew Sartorius, Rodney Wayne Smith +1 more | 2016-10-18 |
| 9424159 | Performance measurement of hardware accelerators | Manoj Dusanapudi, Sairam Kamaraju | 2016-08-23 |
| 9262170 | Out-of-order checkpoint reclamation in a checkpoint processing and recovery core microarchitecture | Ganesh Balakrishnan, Gordon B. Bell | 2016-02-16 |
| 9081504 | Write bandwidth management for flash devices | Ganesh Balakrishnan | 2015-07-14 |
| 9043556 | Optimizing a cache back invalidation policy | Ganesh Balakrishnan | 2015-05-26 |
| 8914570 | Selective write-once-memory encoding in a flash based disk cache memory | Ganesh Balakrishnan | 2014-12-16 |
| 8639886 | Store-to-load forwarding mechanism for processor runahead mode operation | Gordon B. Bell, Srinivasan Ramani | 2014-01-28 |
| 8543767 | Prefetching with multiple processors and threads via a coherency bus | Gordon B. Bell, Gordon Taylor Davis, Jeffrey H. Derby, Srinivasan Ramani, Ken V. Vu +1 more | 2013-09-24 |
| 8438339 | Cache management for a number of threads | Brian M. Rogers | 2013-05-07 |
| 8364898 | Optimizing a cache back invalidation policy | Ganesh Balakrishnan | 2013-01-29 |
| 8200905 | Effective prefetching with multiple processors and threads | Gordon B. Bell, Gordon Taylor Davis, Jeffrey H. Derby, Srinivasan Ramani, Ken V. Vu +1 more | 2012-06-12 |
| 8171220 | Cache architecture with distributed state bits | Ganesh Balakrishnan | 2012-05-01 |
| 8140825 | Systems and methods for selectively closing pages in a memory | Ganesh Balakrishnan, Michael R. Trombley | 2012-03-20 |
| 8140758 | Data reorganization in non-uniform cache access caches | Ganesh Balakrishnan, Gordon B. Bell, Srinivasan Ramani | 2012-03-20 |
| 8140767 | Cache management through delayed writeback | Gordon B. Bell, Brian M. Rogers, Ken V. Vu | 2012-03-20 |
| 8103894 | Power conservation in vertically-striped NUCA caches | Ganesh Balakrishnan | 2012-01-24 |
| 8078852 | Predictors with adaptive prediction threshold | Muawya M. Al-Otoom, Timothy H. Heil, Ken V. Vu | 2011-12-13 |