Issued Patents All Time
Showing 1–25 of 41 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12259789 | Non-volatile memory compression for memory repair | Devanathan Varadarajan, Varun Singh | 2025-03-25 |
| 12197334 | Zero latency prefetching in caches | Oluleye Olorode, Hung Ong | 2025-01-14 |
| 12124374 | Servicing CPU demand requests with inflight prefetches | Oluleye Olorode | 2024-10-22 |
| 12072812 | Highly integrated scalable, flexible DSP megamodule architecture | Timothy David Anderson, Joseph Zbiciak, Duc Quang Bui, Abhijeet Ashok Chachad, Kai Chirca +3 more | 2024-08-27 |
| 11774487 | Electrical and logic isolation for systems on a chip | Jose Luis Flores, Samuel Paul Visalli | 2023-10-03 |
| 11770124 | Integrated circuit with high-speed clock bypass before reset | Jose Luis Flores, Venkateswar Reddy Kowkutla | 2023-09-26 |
| 11748202 | Non-volatile memory compression for memory repair | Devanathan Varadarajan, Varun Singh | 2023-09-05 |
| 11537532 | Lookahead priority collection to support priority elevation | Abhijeet Ashok Chachad, Raguram Damodaran, Joseph Zbiciak | 2022-12-27 |
| 11500777 | Servicing CPU demand requests with inflight prefetches | Oluleye Olorode | 2022-11-15 |
| 11474944 | Zero latency prefetching in caches | Oluleye Olorode, Hung Ong | 2022-10-18 |
| 11436090 | Non-volatile memory compression for memory repair | Devanathan Varadarajan, Varun Singh | 2022-09-06 |
| 11196424 | Integrated circuit with high-speed clock bypass before reset | Jose Luis Flores, Venkateswar Reddy Kowkutla | 2021-12-07 |
| 11036648 | Highly integrated scalable, flexible DSP megamodule architecture | Timothy David Anderson, Joseph Zbiciak, Duc Quang Bui, Abhijeet Ashok Chachad, Kai Chirca +3 more | 2021-06-15 |
| 10929296 | Zero latency prefetching in caches | Oluleye Olorode, Hung Ong | 2021-02-23 |
| 10713180 | Lookahead priority collection to support priority elevation | Abhijeet Ashok Chachad, Raguram Damodaran, Joseph Zbiciak | 2020-07-14 |
| 10558578 | Servicing CPU demand requests with inflight prefetches | Oluleye Olorode | 2020-02-11 |
| 10509718 | System and method for automatically generating software testing scripts from test cases | Amarnath Sankar, Carnelian Lamech, Ghatak Anit, Srinivasan Kumarappan, Suraj Sangavkar | 2019-12-17 |
| 10210090 | Servicing CPU demand requests with inflight prefetchs | Oluleye Olorode | 2019-02-19 |
| 10162641 | Highly integrated scalable, flexible DSP megamodule architecture | Timothy David Anderson, Joseph Zbiciak, Duc Quang Bui, Abhijeet Ashok Chachad, Kai Chirca +3 more | 2018-12-25 |
| 9798344 | Power switch with source-bias mode for on-chip powerdomain supply drooping | Shane Stelmach, Soman Purushotaman, Michael J. Gill, Jose Luis Flores | 2017-10-24 |
| 9652402 | Hiding page translation miss latency in program memory controller by next page prefetch on crossing page boundary | Oluleye Olorode | 2017-05-16 |
| 9652392 | Using L1 cache as re-order buffer | Oluleye Olorode, Hung Ong | 2017-05-16 |
| 9618956 | On-chip power-domain supply drooping for low voltage idle/standby management | Michael J. Gill, Shane Stelmach, Jose Luis Flores | 2017-04-11 |
| 9606803 | Highly integrated scalable, flexible DSP megamodule architecture | Timothy David Anderson, Joseph Zbiciak, Duc Quang Bui, Abhijeet Ashok Chachad, Kai Chirca +3 more | 2017-03-28 |
| 9557936 | Protection of memories, datapath and pipeline registers, and other storage elements by distributed delayed detection and correction of soft errors | Timothy David Anderson, Joseph Zbiciak, Abhijeet Ashok Chachad, Kai Chirca, Naveen Bhoria +2 more | 2017-01-31 |