Issued Patents All Time
Showing 26–41 of 41 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9514058 | Local page translation and permissions storage for the page window in program memory controller | Oluleye Olorode | 2016-12-06 |
| 9514059 | Hiding page translation miss latency in program memory controller by selective page miss translation prefetch | Oluleye Olorode, Bipin Prasad Heremagalur Ramaprasad | 2016-12-06 |
| 9471320 | Using L1 cache as re-order buffer | Oluleye Olorode, Hung Ong | 2016-10-18 |
| 9417648 | Power switch with source-bias mode for on-chip powerdomain supply drooping | Shane Stelmach, Soman Purushotaman, Michael J. Gill, Jose Luis Flores | 2016-08-16 |
| 9264497 | System and method for hosting mobile devices for testing in a cloud computing environment | Somasundaram Jambunathan | 2016-02-16 |
| 8977878 | Reducing current leakage in L1 program memory | Hung Ong | 2015-03-10 |
| 8970267 | Asynchronous clock dividers to reduce on-chip variations of clock timing | Raguram Damodaran, Abhijeet Ashok Chachad | 2015-03-03 |
| 8862836 | Multi-port register file with an input pipelined architecture with asynchronous reads and localized feedback | Raguram Damodaran, Naveen Bhoria | 2014-10-14 |
| 8732416 | Requester based transaction status reporting in a system with multi-level memory | Raguram Damodaran, Abhijeet Ashok Chachad, Dheera Balasubramanian, Naveen Bhoria | 2014-05-20 |
| 8694843 | Clock control of pipelined memory for improved delay fault testing | Sumant Dinkar Kale, Abhijeet Ashok Chachad | 2014-04-08 |
| 8661199 | Efficient level two memory banking to improve performance for multiple source traffic and enable deeper pipelining of accesses by reducing bank stalls | Abhijeet Ashok Chachad | 2014-02-25 |
| 8598932 | Integer and half clock step division digital variable clock divider | Anthony Lell, Raguram Damodaran | 2013-12-03 |
| 8582384 | Process variability tolerant programmable memory controller for a pipelined memory system | Abhijeet Ashok Chachad, Raguram Damodaran | 2013-11-12 |
| 8532247 | Integer and half clock step division digital variable clock divider | Anthony Lell, Raguram Damodaran | 2013-09-10 |
| 8488405 | Process variability tolerant programmable memory controller for a pipelined memory system | Abhijeet Ashok Chachad, Raguram Damodaran | 2013-07-16 |
| 8375265 | Delay fault testing using distributed clock dividers | Alan Hales, William Cronin Wallace | 2013-02-12 |