Issued Patents All Time
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12223100 | Hardware protection of inline cryptographic processor | Amritpal Singh Mundra | 2025-02-11 |
| 12086632 | Real-time context specific task manager for multi-core communication and control system | Thomas Anton Leyrer | 2024-09-10 |
| 11966777 | Level two first-in-first-out transmission | Thomas Anton Leyrer, David Alston Lide | 2024-04-23 |
| 11875183 | Real-time arbitration of shared resources in a multi-master communication and control system | Thomas Anton Leyrer | 2024-01-16 |
| 11726814 | Resource availability management using real-time task manager in multi-core system | Anjandeep Singh SAHNI, Pratheesh Gangadhar Thalakkal Kottilaveedu | 2023-08-15 |
| 11704154 | High-speed broadside communications and control system | Thomas Anton Leyrer, Pratheesh Gangadhar Thalakkal Kottilaveedu, David Alston Lide | 2023-07-18 |
| 11579877 | Broadside random access memory for low cycle memory access and additional functions | Thomas Anton Leyrer, David Alston Lide, Pratheesh Gangadhar Thalakkal Kottilaveedu | 2023-02-14 |
| 11343205 | Real-time, time aware, dynamic, context aware and reconfigurable ethernet packet classification | Thomas Anton Leyrer, Pratheesh Gangadhar Thalakkal Kottilaveedu | 2022-05-24 |
| 11290099 | Managing pulse-width modulation trip signals from multiple sources | Thomas Anton Leyrer, Martin Staebler | 2022-03-29 |
| 11281493 | Real-time context specific task manager for multi-core communication and control system | Thomas Anton Leyrer | 2022-03-22 |
| 11243809 | Level two first-in-first-out transmission | Thomas Anton Leyrer, David Alston Lide | 2022-02-08 |
| 11048552 | High-speed broadside communications and control system | Thomas Anton Leyrer, Pratheesh Gangadhar Thalakkal Kottilaveedu, David Alston Lide | 2021-06-29 |
| 10970074 | Broadside random access memory for low cycle memory access and additional functions | Thomas Anton Leyrer, David Alston Lide, Pratheesh Gangadhar Thalakkal K{dot over (o)}ttilaveedu | 2021-04-06 |
| 10891717 | Adaptive bilateral (BL) filtering for computer vision | Mihir Narendra Mody, Shashank Dabral, Jesse Gregory Villarreal, Jr., Niraj Nandan | 2021-01-12 |
| 10871992 | Level two first-in-first-out transmission | Thomas Anton Leyrer, David Alston Lide | 2020-12-22 |
| 10812060 | Managing pulse-width modulation trip signals from multiple sources | Thomas Anton Leyrer, Martin Staebler | 2020-10-20 |
| 10121231 | Adaptive bilateral (BL) filtering for computer vision | Mihir Narendra Mody, Shashank Dabral, Jesse Gregory Villarreal, Jr., Niraj Nandan | 2018-11-06 |
| 9303953 | Digital system for the detection of variations in operating conditions of an integrated circuit | Alok Anand, Ravi Srivaths, Chillara Kiran Kumar, Aruna Koityar | 2016-04-05 |
| 9153295 | Register bank cross path connection method in a multi core processor system | Pratheesh Gangadhar Thalakkal Kottilaveedu | 2015-10-06 |
| 8902922 | Unified programmable interface for real-time Ethernet | Maneesh Soni | 2014-12-02 |
| 8375265 | Delay fault testing using distributed clock dividers | Ramakrishnan Venkatasubramanian, Alan Hales | 2013-02-12 |