Issued Patents All Time
Showing 25 most recent of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12113612 | Apparatus and mechanism to support multiple time domains in a single SoC for time sensitive network | Chunhua Hu, Venkateswar Reddy Kowkutla, Eric Hansen, Denis Beaudoin | 2024-10-08 |
| 12086632 | Real-time context specific task manager for multi-core communication and control system | William Cronin Wallace | 2024-09-10 |
| 12040885 | Open real-time ethernet protocol | Thomas Mauer | 2024-07-16 |
| 11966777 | Level two first-in-first-out transmission | William Cronin Wallace, David Alston Lide | 2024-04-23 |
| 11875183 | Real-time arbitration of shared resources in a multi-master communication and control system | William Cronin Wallace | 2024-01-16 |
| 11704154 | High-speed broadside communications and control system | William Cronin Wallace, Pratheesh Gangadhar Thalakkal Kottilaveedu, David Alston Lide | 2023-07-18 |
| 11579877 | Broadside random access memory for low cycle memory access and additional functions | William Cronin Wallace, David Alston Lide, Pratheesh Gangadhar Thalakkal Kottilaveedu | 2023-02-14 |
| 11405121 | Apparatus and mechanism to support multiple time domains in a single SoC for time sensitive network | Chunhua Hu, Venkateswar Reddy Kowkutla, Eric Hansen, Denis Beaudoin | 2022-08-02 |
| 11343205 | Real-time, time aware, dynamic, context aware and reconfigurable ethernet packet classification | William Cronin Wallace, Pratheesh Gangadhar Thalakkal Kottilaveedu | 2022-05-24 |
| 11336757 | Sample based data transmission over low-level communication channel | Peter Aberl | 2022-05-17 |
| 11290099 | Managing pulse-width modulation trip signals from multiple sources | Martin Staebler, William Cronin Wallace | 2022-03-29 |
| 11281493 | Real-time context specific task manager for multi-core communication and control system | William Cronin Wallace | 2022-03-22 |
| 11243809 | Level two first-in-first-out transmission | William Cronin Wallace, David Alston Lide | 2022-02-08 |
| 11075707 | Open real-time ethernet protocol | Thomas Mauer | 2021-07-27 |
| 11048552 | High-speed broadside communications and control system | William Cronin Wallace, Pratheesh Gangadhar Thalakkal Kottilaveedu, David Alston Lide | 2021-06-29 |
| 10970074 | Broadside random access memory for low cycle memory access and additional functions | William Cronin Wallace, David Alston Lide, Pratheesh Gangadhar Thalakkal K{dot over (o)}ttilaveedu | 2021-04-06 |
| 10871992 | Level two first-in-first-out transmission | William Cronin Wallace, David Alston Lide | 2020-12-22 |
| 10812060 | Managing pulse-width modulation trip signals from multiple sources | Martin Staebler, William Cronin Wallace | 2020-10-20 |
| 10484119 | Open real-time ethernet protocol | Thomas Mauer | 2019-11-19 |
| 10396922 | Apparatus and mechanism to support multiple time domains in a single soc for time sensitive network | Chunhua Hu, Venkateswar Reddy Kowkutla, Eric Hansen, Denis Beaudoin | 2019-08-27 |
| 8130791 | Receiver and method for processing a stream of data packets when an error occurred on the physical layer | Krzysztof Chruscinski | 2012-03-06 |
| 6948013 | Apparatus and method for configuring data cells | — | 2005-09-20 |
| 6707902 | Method of resynchronizing data transfer between two modems connected by a dedicated line | Umashankar Iyer, Sharmila Kannangara | 2004-03-16 |
| 5860027 | System for receiving burst width greater than cache width by storing first portion of burst to cache and storing second portion of burst to storage circuit | Steven D. Sabin | 1999-01-12 |
| 5729713 | Data processing with first level cache bypassing after a data transfer becomes excessively long | — | 1998-03-17 |