| 12204393 |
Integrated circuit with debugger and arbitration interface |
Jose Luis Flores, Gary A. Cooper, Amritpal Singh Mundra, Jason Lynn Peck |
2025-01-21 |
| 12204425 |
Debug for multi-threaded processing |
Niraj Nandan, Hetul Sanghvi, Mihir Narendra Mody, Gary A. Cooper |
2025-01-21 |
| 12111778 |
Image processing accelerator |
Mihir Narendra Mody, Niraj Nandan, Hetul Sanghvi, Brian Chae, Rajasekhar Reddy Allu +2 more |
2024-10-08 |
| 11927629 |
Global time counter based debug |
Pandy Kalimuthu |
2024-03-12 |
| 11847006 |
Integrated circuit with debugger and arbitration interface |
Jose Luis Flores, Gary A. Cooper, Amritpal Singh Mundra, Jason Lynn Peck |
2023-12-19 |
| 11798128 |
Robust frame size error detection and recovery mechanism to minimize frame loss for camera input sub-systems |
Brian Chae, Niraj Nandan, Mihir Narendra Mody |
2023-10-24 |
| 11789836 |
Debug for multi-threaded processing |
Niraj Nandan, Hetul Sanghvi, Mihir Narendra Mody, Gary A. Cooper |
2023-10-17 |
| 11447071 |
Flexible hub for handling multi-sensor data |
Rajat Sagar, Mihir Narendra Mody, Gregory Raymond Shurtz |
2022-09-20 |
| 11276134 |
Reconfigurable image processing hardware pipeline |
Mihir Narendra Mody, Niraj Nandan, Rajat Sagar, Shashank Dabral, Brijesh Rameshbhai Jadav |
2022-03-15 |
| 11237991 |
Image processing accelerator |
Mihir Narendra Mody, Niraj Nandan, Hetul Sanghvi, Brian Chae, Rajasekhar Reddy Allu +2 more |
2022-02-01 |
| 11144417 |
Debug for multi-threaded processing |
Niraj Nandan, Hetul Sanghvi, Mihir Narendra Mody, Gary A. Cooper |
2021-10-12 |
| 11027656 |
Flexible hub for handling multi-sensor data |
Rajat Sagar, Mihir Narendra Mody, Gregory Raymond Shurtz |
2021-06-08 |
| 10747692 |
Image processing accelerator |
Mihir Narendra Mody, Niraj Nandan, Hetul Sanghvi, Brian Chae, Rajasekhar Reddy Allu +2 more |
2020-08-18 |
| 9871965 |
Image processing for wide dynamic range (WDR) sensor data |
Shashank Dabral, Mihir Narendra Mody, Gang Hua, Niraj Nandan, Rajashekhar Allu |
2018-01-16 |
| 8598932 |
Integer and half clock step division digital variable clock divider |
Ramakrishnan Venkatasubramanian, Raguram Damodaran |
2013-12-03 |
| 8532247 |
Integer and half clock step division digital variable clock divider |
Ramakrishnan Venkatasubramanian, Raguram Damodaran |
2013-09-10 |
| 7917753 |
Transferring control between programs of different security levels |
Michael D. Asal, Gary L. Swoboda |
2011-03-29 |
| 7698544 |
Automatic halting of a processor in debug mode due to reset |
Michael D. Asal, Gary L. Swoboda |
2010-04-13 |
| 6055649 |
Processor test port with scan chains and data streaming |
Douglas E. Deao, Natarajan Seshan |
2000-04-25 |
| 5970241 |
Maintaining synchronism between a processor pipeline and subsystem pipelines during debugging of a data processing system |
Douglas E. Deao, Natarajan Seshan |
1999-10-19 |