Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
JT

Jonathan (Son) Hung Tran — 33 Patents

TITexas Instruments: 20 patents #614 of 12,488Top 5%
MCMcafee: 5 patents #230 of 1,127Top 25%
NTNetworks Associates Technology: 5 patents #6 of 189Top 4%
CSCapital One Services: 2 patents #1,381 of 2,893Top 50%
MEMetawork: 1 patents #26 of 97Top 30%
Sachse, TX: #12 of 446 inventorsTop 3%
Texas: #3,395 of 125,132 inventorsTop 3%
Overall (All Time): #105,480 of 4,157,543Top 3%
33 Patents All Time
Jonathan (Son) Hung Tran has been granted 33 US patents while listed as an inventor at Texas Instruments. The first was granted in 2000 and the most recent in July 2024. Jonathan (Son) Hung Tran ranks #105,480 of 4,157,543 US inventors in our database (top 2.5%). Patent records list Jonathan (Son) Hung Tran in Sachse, TX, US.

Issued Patents All Time

Showing 1–25 of 33 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12050914 Cache management operations using streaming engine Joseph Zbiciak, Timothy David Anderson, Kai Chirca, Daniel Wu, Abhijeet Ashok Chachad +1 more 2024-07-30 $47,336,000
12045616 Storage organization for transposing a matrix using a streaming engine Joseph Zbiciak 2024-07-23 $32,250,000
11900117 Mechanism to queue multiple streams to run on streaming engine Timothy David Anderson, Joseph Zbiciak 2024-02-13 $26,003,000
11790249 Automatically evaluating application architecture through architecture-as-code Zachary Blizzard, Christopher John Ocampo, Tanusree McCabe, Bradley Clarke Dellinger, Bita Akhlaghi +12 more 2023-10-17 $8,434,000
11526775 Automatically evaluating application architecture through architecture-as-code Zachary Blizzard, Christopher John Ocampo, Tanusree McCabe, Bradley Clarke Dellinger, Bita Akhlaghi +12 more 2022-12-13 $50,645,000
11307858 Cache preload operations using streaming engine Joseph Zbiciak, Timothy David Anderson, Kai Chirca, Daniel Wu, Abhijeet Ashok Chachad +1 more 2022-04-19 $45,950,000
11119776 Cache management operations using streaming engine Joseph Zbiciak, Timothy David Anderson, Kai Chirca, Daniel Wu, Abhijeet Ashok Chachad +1 more 2021-09-14 $36,977,000
10963254 Mechanism to queue multiple streams to run on streaming engine Timothy David Anderson, Joseph Zbiciak 2021-03-30 $42,681,000
10949206 Transposing a matrix using a streaming engine Joseph Zbiciak 2021-03-16 $58,029,000
10942741 Storage organization for transposing a matrix using a streaming engine Joseph Zbiciak 2021-03-09 $64,498,000
10606596 Cache preload operations using streaming engine Joseph Zbiciak, Timothy David Anderson, Kai Chirca, Daniel Wu, Abhijeet Ashok Chachad +1 more 2020-03-31 $21,150,000
10599433 Cache management operations using streaming engine Joseph Zbiciak, Timothy David Anderson, Kai Chirca, Daniel Wu, Abhijeet Ashok Chachad +1 more 2020-03-24 $17,530,000
9557936 Protection of memories, datapath and pipeline registers, and other storage elements by distributed delayed detection and correction of soft errors Timothy David Anderson, Joseph Zbiciak, Abhijeet Ashok Chachad, Kai Chirca, Naveen Bhoria +2 more 2017-01-31 $22,242,000
9298643 Performance and power improvement on DMA writes to level two combined cache/SRAM that is cached in level one data cache and line is valid and dirty Raguram Damodaran, Abhijeet Ashok Chachad, Joseph Zbiciak 2016-03-29 $25,607,000
9292273 Software uninstallation system, method and computer program product William Cheng, Kenneth Hwang, Ravi Kannan, Babu Katchapalayam, Bing Liu +2 more 2016-03-22
9268708 Level one data cache line lock and enhanced snoop protocol during cache victims and writebacks to maintain level one data cache and level two cache coherence Raguram Damodaran, Abhijeet Ashok Chachad, David Matthew Thompson 2016-02-23 $13,969,000
9075744 Performance and power improvement on DMA writes to level two combined cache/SRAM that is caused in level one data cache and line is valid and dirty Raguram Damodaran, Abhijeet Ashok Chachad, Joseph Zbiciak 2015-07-07 $9,588,000
9003122 Level one data cache line lock and enhanced snoop protocol during cache victims and writebacks to maintain level one data cache and level two cache coherence Raguram Damodaran, Abhijeet Ashok Chachad, David Matthew Thompson 2015-04-07 $7,585,000
8904115 Cache with multiple access pipelines Abhijeet Ashok Chachad, Raguram Damodaran, Timothy David Anderson, Sanjive Agarwala 2014-12-02 $13,699,000
8904260 Robust hamming code implementation for soft error detection, correction, and reporting in a multi-level cache system using dual banking memory scheme Abhijeet Ashok Chachad, Joseph Zbiciak, Krishna Chaithanya Gurram 2014-12-02 $13,699,000
8856446 Hazard prevention for data conflicts between level one data cache line allocates and snoop writes Abhijeet Ashok Chachad, Raguram Damodaran, Krishna Chaithanya Gurram 2014-10-07 $8,794,000
8707127 Configurable source based/requestor based error detection and correction for soft errors in multi-level cache memory to minimize CPU interrupt service routines Abhijeet Ashok Chachad, Raguram Damodaran, Krishna Chaithanya Gurram 2014-04-22 $8,414,000
8656105 Optimizing tag forwarding in a two level cache system from level one to lever two controllers for cache coherence protocol for direct memory access transfers Raguram Damodaran, Abhijeet Ashok Chachad, Joseph Zbiciak 2014-02-18 $7,619,000
8533703 Information processing apparatus, and system having preview control, and method thereof, and storage medium storing program for implementing the method William Cheng, Kenneth Hwang, Ravi Kannan, Babu Katchapalayam, Bing Liu +2 more 2013-09-10
8527977 Software uninstallation system, method and computer program product William Cheng, Kenneth Hwang, Ravi Kannan, Babu Katchapalayam, Bing Liu +2 more 2013-09-03