Issued Patents All Time
Showing 25 most recent of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12050914 | Cache management operations using streaming engine | Joseph Zbiciak, Timothy David Anderson, Kai Chirca, Daniel Wu, Abhijeet Ashok Chachad +1 more | 2024-07-30 |
| 12045616 | Storage organization for transposing a matrix using a streaming engine | Joseph Zbiciak | 2024-07-23 |
| 11900117 | Mechanism to queue multiple streams to run on streaming engine | Timothy David Anderson, Joseph Zbiciak | 2024-02-13 |
| 11790249 | Automatically evaluating application architecture through architecture-as-code | Zachary Blizzard, Christopher John Ocampo, Tanusree McCabe, Bradley Clarke Dellinger, Bita Akhlaghi +12 more | 2023-10-17 |
| 11526775 | Automatically evaluating application architecture through architecture-as-code | Zachary Blizzard, Christopher John Ocampo, Tanusree McCabe, Bradley Clarke Dellinger, Bita Akhlaghi +12 more | 2022-12-13 |
| 11307858 | Cache preload operations using streaming engine | Joseph Zbiciak, Timothy David Anderson, Kai Chirca, Daniel Wu, Abhijeet Ashok Chachad +1 more | 2022-04-19 |
| 11119776 | Cache management operations using streaming engine | Joseph Zbiciak, Timothy David Anderson, Kai Chirca, Daniel Wu, Abhijeet Ashok Chachad +1 more | 2021-09-14 |
| 10963254 | Mechanism to queue multiple streams to run on streaming engine | Timothy David Anderson, Joseph Zbiciak | 2021-03-30 |
| 10949206 | Transposing a matrix using a streaming engine | Joseph Zbiciak | 2021-03-16 |
| 10942741 | Storage organization for transposing a matrix using a streaming engine | Joseph Zbiciak | 2021-03-09 |
| 10606596 | Cache preload operations using streaming engine | Joseph Zbiciak, Timothy David Anderson, Kai Chirca, Daniel Wu, Abhijeet Ashok Chachad +1 more | 2020-03-31 |
| 10599433 | Cache management operations using streaming engine | Joseph Zbiciak, Timothy David Anderson, Kai Chirca, Daniel Wu, Abhijeet Ashok Chachad +1 more | 2020-03-24 |
| 9557936 | Protection of memories, datapath and pipeline registers, and other storage elements by distributed delayed detection and correction of soft errors | Timothy David Anderson, Joseph Zbiciak, Abhijeet Ashok Chachad, Kai Chirca, Naveen Bhoria +2 more | 2017-01-31 |
| 9298643 | Performance and power improvement on DMA writes to level two combined cache/SRAM that is cached in level one data cache and line is valid and dirty | Raguram Damodaran, Abhijeet Ashok Chachad, Joseph Zbiciak | 2016-03-29 |
| 9292273 | Software uninstallation system, method and computer program product | William Cheng, Kenneth Hwang, Ravi Kannan, Babu Katchapalayam, Bing Liu +2 more | 2016-03-22 |
| 9268708 | Level one data cache line lock and enhanced snoop protocol during cache victims and writebacks to maintain level one data cache and level two cache coherence | Raguram Damodaran, Abhijeet Ashok Chachad, David Matthew Thompson | 2016-02-23 |
| 9075744 | Performance and power improvement on DMA writes to level two combined cache/SRAM that is caused in level one data cache and line is valid and dirty | Raguram Damodaran, Abhijeet Ashok Chachad, Joseph Zbiciak | 2015-07-07 |
| 9003122 | Level one data cache line lock and enhanced snoop protocol during cache victims and writebacks to maintain level one data cache and level two cache coherence | Raguram Damodaran, Abhijeet Ashok Chachad, David Matthew Thompson | 2015-04-07 |
| 8904115 | Cache with multiple access pipelines | Abhijeet Ashok Chachad, Raguram Damodaran, Timothy David Anderson, Sanjive Agarwala | 2014-12-02 |
| 8904260 | Robust hamming code implementation for soft error detection, correction, and reporting in a multi-level cache system using dual banking memory scheme | Abhijeet Ashok Chachad, Joseph Zbiciak, Krishna Chaithanya Gurram | 2014-12-02 |
| 8856446 | Hazard prevention for data conflicts between level one data cache line allocates and snoop writes | Abhijeet Ashok Chachad, Raguram Damodaran, Krishna Chaithanya Gurram | 2014-10-07 |
| 8707127 | Configurable source based/requestor based error detection and correction for soft errors in multi-level cache memory to minimize CPU interrupt service routines | Abhijeet Ashok Chachad, Raguram Damodaran, Krishna Chaithanya Gurram | 2014-04-22 |
| 8656105 | Optimizing tag forwarding in a two level cache system from level one to lever two controllers for cache coherence protocol for direct memory access transfers | Raguram Damodaran, Abhijeet Ashok Chachad, Joseph Zbiciak | 2014-02-18 |
| 8533703 | Information processing apparatus, and system having preview control, and method thereof, and storage medium storing program for implementing the method | William Cheng, Kenneth Hwang, Ravi Kannan, Babu Katchapalayam, Bing Liu +2 more | 2013-09-10 |
| 8527977 | Software uninstallation system, method and computer program product | William Cheng, Kenneth Hwang, Ravi Kannan, Babu Katchapalayam, Bing Liu +2 more | 2013-09-03 |