Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Protection of memories, datapath and pipeline registers, and other storage elements by distributed delayed detection and correction of soft errors

Protection of memories, datapath and pipeline registers, and other storage elements by distributed delayed detection and correction of soft errors

US Patent 9557936 · Granted Jan 31, 2017

Estimated economic value: $22,242,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Pipelined read-modify-write operations in cache memory2025
Register file structures combining vector and scalar data with global and local 2025
Register file structures combining vector and scalar data with global and local 2025
Write control for read-modify-write operations in cache memory2025
Write control for read-modify-write operations in cache memory2025
Vector maximum and minimum with indexing2025
Method and apparatus for implied bit handling in floating point multiplication2025
Streaming engine with early exit from loop levels supporting early exit loops an2025
Converting a stream of data using a lookaside buffer2025
Controller with caching and non-caching modes2025
Controller with caching and non-caching modes2025
System and method to control the number of active vector lanes in a processor2025