Issued Patents All Time
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8904260 | Robust hamming code implementation for soft error detection, correction, and reporting in a multi-level cache system using dual banking memory scheme | Jonathan (Son) Hung Tran, Abhijeet Ashok Chachad, Joseph Zbiciak | 2014-12-02 |
| 8856446 | Hazard prevention for data conflicts between level one data cache line allocates and snoop writes | Abhijeet Ashok Chachad, Jonathan (Son) Hung Tran, Raguram Damodaran | 2014-10-07 |
| 8707127 | Configurable source based/requestor based error detection and correction for soft errors in multi-level cache memory to minimize CPU interrupt service routines | Jonathan (Son) Hung Tran, Abhijeet Ashok Chachad, Raguram Damodaran | 2014-04-22 |