Issued Patents All Time
Showing 25 most recent of 31 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8904115 | Cache with multiple access pipelines | Abhijeet Ashok Chachad, Raguram Damodaran, Jonathan (Son) Hung Tran, Timothy David Anderson | 2014-12-02 |
| 7716388 | Command re-ordering in hub interface unit based on priority | Shoban Srikrishna Jagathesan, Kyle Castille, Quang Dieu An | 2010-05-11 |
| 7673076 | Concurrent read response acknowledge enhanced direct memory access unit | Kyle Castille, Quang Dieu An | 2010-03-02 |
| 7603487 | Hardware configurable hub interface unit | Shoban Srikrishna Jagathesan, Raguram Damodaran | 2009-10-13 |
| 7577774 | Independent source read and destination write enhanced DMA | Kyle Castille, Quang Dieu An, Hung Ong | 2009-08-18 |
| 7325178 | Programmable built in self test of memory | Raguram Damodaran, Timothy David Anderson, Joel J. Graber | 2008-01-29 |
| 7095671 | Electrical fuse control of memory slowdown | Manjeri Krishnan, Bryan Sheffield, Joel J. Graber, Duy-Loan T. Le | 2006-08-22 |
| 7047284 | Transfer request bus node for transfer controller with hub and ports | David A. Comisky, Charles Fuoco, Iain Robertson, David Hoyle, John D. Keay +3 more | 2006-05-16 |
| 6985982 | Active ports in a transfer controller with hub and ports | David A. Comisky, Charles Fuoco, Raguram Damodaran | 2006-01-10 |
| 6954468 | Write allocation counter for transfer controller with hub and ports | Iain Robertson, David A. Comisky, Charles Fuoco | 2005-10-11 |
| 6928011 | Electrical fuse control of memory slowdown | Manjeri Krishnan, Bryan Sheffield, Joel J. Graber, Duy-Loan T. Le | 2005-08-09 |
| 6868087 | Request queue manager in transfer controller with hub and ports | Iain Robertson, David A. Comisky, Charles Fuoco, Christopher L. Mobley | 2005-03-15 |
| 6694385 | Configuration bus reconfigurable/reprogrammable interface for expanded direct memory access processor | Charles Fuoco, David A. Comisky | 2004-02-17 |
| 6681270 | Effective channel priority processing for transfer controller with hub and ports | Iain Robertson, David A. Comisky | 2004-01-20 |
| 6665767 | Programmer initiated cache block operations | David A. Comisky, Timothy David Anderson, Charles Fuoco | 2003-12-16 |
| 6658503 | Parallel transfer size calculation and annulment determination in transfer controller with hub and ports | Iain Robertson, David A. Comisky | 2003-12-02 |
| 6654819 | External direct memory access processor interface to centralized transaction processor | David A. Comisky, Iain Robertson | 2003-11-25 |
| 6622181 | Timing window elimination in self-modifying direct memory access processors | David A. Comisky | 2003-09-16 |
| 6606686 | Unified memory system architecture including cache and directly addressable static random access memory | Charles Fuoco, David A. Comisky, Timothy David Anderson, Christopher L. Mobley | 2003-08-12 |
| 6594711 | Method and apparatus for operating one or more caches in conjunction with direct memory access controller | Timothy David Anderson, Charles Fuoco, David A. Comisky | 2003-07-15 |
| 6594713 | Hub interface unit and application unit interfaces for expanded direct memory access processor | Charles Fuoco, David A. Comisky, Raguram Damodaran | 2003-07-15 |
| 6535958 | Multilevel cache system coherence with memory selectively configured as cache or direct access memory and direct memory access | Charles Fuoco, David A. Comisky, Timothy David Anderson, Christopher L. Mobley | 2003-03-18 |
| 6484237 | Unified multilevel memory system architecture which supports both cache and addressable SRAM | Charles Fuoco, David A. Comisky, Timothy David Anderson | 2002-11-19 |
| 6446241 | Automated method for testing cache | Christopher L. Mobley, Timothy David Anderson, Charles Fuoco | 2002-09-03 |
| 6408345 | Superscalar memory transfer controller in multilevel memory organization | Charles Fuoco, David A. Comisky, Christopher L. Mobley | 2002-06-18 |