Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9715468 | Method of providing timing information for interrupts | Bradley James Griffis, Merrill Ray Newman | 2017-07-25 |
| 7630841 | Supervising and sequencing commonly driven power supplies with digital information | Brandon Christopher Azbell, Bradley James Griffis | 2009-12-08 |
| 7050552 | System and method to mitigate pots ringing interference in DSL | — | 2006-05-23 |
| 7047284 | Transfer request bus node for transfer controller with hub and ports | Sanjive Agarwala, Charles Fuoco, Iain Robertson, David Hoyle, John D. Keay +3 more | 2006-05-16 |
| 6985982 | Active ports in a transfer controller with hub and ports | Sanjive Agarwala, Charles Fuoco, Raguram Damodaran | 2006-01-10 |
| 6954468 | Write allocation counter for transfer controller with hub and ports | Sanjive Agarwala, Iain Robertson, Charles Fuoco | 2005-10-11 |
| 6868087 | Request queue manager in transfer controller with hub and ports | Sanjive Agarwala, Iain Robertson, Charles Fuoco, Christopher L. Mobley | 2005-03-15 |
| 6801985 | Data bus using synchronous fixed latency loop including read address and data busses and write address and data busses | Joseph Zbiciak | 2004-10-05 |
| 6694385 | Configuration bus reconfigurable/reprogrammable interface for expanded direct memory access processor | Charles Fuoco, Sanjive Agarwala | 2004-02-17 |
| 6681270 | Effective channel priority processing for transfer controller with hub and ports | Sanjive Agarwala, Iain Robertson | 2004-01-20 |
| 6665767 | Programmer initiated cache block operations | Sanjive Agarwala, Timothy David Anderson, Charles Fuoco | 2003-12-16 |
| 6658503 | Parallel transfer size calculation and annulment determination in transfer controller with hub and ports | Sanjive Agarwala, Iain Robertson | 2003-12-02 |
| 6654819 | External direct memory access processor interface to centralized transaction processor | Iain Robertson, Sanjive Agarwala | 2003-11-25 |
| 6629187 | Cache memory controlled by system address properties | Steven D. Krueger | 2003-09-30 |
| 6622181 | Timing window elimination in self-modifying direct memory access processors | Sanjive Agarwala | 2003-09-16 |
| 6606686 | Unified memory system architecture including cache and directly addressable static random access memory | Sanjive Agarwala, Charles Fuoco, Timothy David Anderson, Christopher L. Mobley | 2003-08-12 |
| 6594711 | Method and apparatus for operating one or more caches in conjunction with direct memory access controller | Timothy David Anderson, Sanjive Agarwala, Charles Fuoco | 2003-07-15 |
| 6594713 | Hub interface unit and application unit interfaces for expanded direct memory access processor | Charles Fuoco, Sanjive Agarwala, Raguram Damodaran | 2003-07-15 |
| 6574683 | External direct memory access processor implementation that includes a plurality of priority levels stored in request queue | Iain Robertson | 2003-06-03 |
| 6535958 | Multilevel cache system coherence with memory selectively configured as cache or direct access memory and direct memory access | Charles Fuoco, Sanjive Agarwala, Timothy David Anderson, Christopher L. Mobley | 2003-03-18 |
| 6484237 | Unified multilevel memory system architecture which supports both cache and addressable SRAM | Sanjive Agarwala, Charles Fuoco, Timothy David Anderson | 2002-11-19 |
| 6408345 | Superscalar memory transfer controller in multilevel memory organization | Charles Fuoco, Sanjive Agarwala, Christopher L. Mobley | 2002-06-18 |