Issued Patents All Time
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7047284 | Transfer request bus node for transfer controller with hub and ports | Sanjive Agarwala, David A. Comisky, Charles Fuoco, Iain Robertson, David Hoyle +3 more | 2006-05-16 |
| 6868087 | Request queue manager in transfer controller with hub and ports | Sanjive Agarwala, Iain Robertson, David A. Comisky, Charles Fuoco | 2005-03-15 |
| 6606686 | Unified memory system architecture including cache and directly addressable static random access memory | Sanjive Agarwala, Charles Fuoco, David A. Comisky, Timothy David Anderson | 2003-08-12 |
| 6535958 | Multilevel cache system coherence with memory selectively configured as cache or direct access memory and direct memory access | Charles Fuoco, Sanjive Agarwala, David A. Comisky, Timothy David Anderson | 2003-03-18 |
| 6446241 | Automated method for testing cache | Timothy David Anderson, Charles Fuoco, Sanjive Agarwala | 2002-09-03 |
| 6408345 | Superscalar memory transfer controller in multilevel memory organization | Charles Fuoco, Sanjive Agarwala, David A. Comisky | 2002-06-18 |