| 9103886 |
Delay testing capturing second response to first response as stimulus |
Lee D. Whetsel |
2015-08-11 |
| 8683281 |
Scan path delay testing with two memories and three subdivisions |
Lee D. Whetsel |
2014-03-25 |
| 8356220 |
Memory coupling scan input to first of scan path segments |
Lee D. Whetsel |
2013-01-15 |
| 8185789 |
Capturing response after simultaneously inputting last stimulus bit in scan path subdivisions |
Lee D. Whetsel |
2012-05-22 |
| 8015464 |
Segmented scan paths with cache bit memory inputs |
Lee D. Whetsel |
2011-09-06 |
| 7795918 |
Adjusting output buffer timing based on drive strength |
— |
2010-09-14 |
| 7437639 |
Response bits as stimulus in subdivided scan path delay test |
Lee D. Whetsel |
2008-10-14 |
| 7325178 |
Programmable built in self test of memory |
Raguram Damodaran, Timothy David Anderson, Sanjive Agarwala |
2008-01-29 |
| 7095671 |
Electrical fuse control of memory slowdown |
Manjeri Krishnan, Bryan Sheffield, Duy-Loan T. Le, Sanjive Agarwala |
2006-08-22 |
| 6928011 |
Electrical fuse control of memory slowdown |
Manjeri Krishnan, Bryan Sheffield, Duy-Loan T. Le, Sanjive Agarwala |
2005-08-09 |
| 6898749 |
IC with cache bit memory in series with scan segment |
Lee D. Whetsel |
2005-05-24 |
| 6065113 |
Circuits, systems, and methods for uniquely identifying a microprocessor at the instruction set level employing one-time programmable register |
Jonathan H. Shiell, Donald E. Steiss |
2000-05-16 |
| 6061811 |
Circuits, systems, and methods for external evaluation of microprocessor built-in self-test |
James O. Bondi, Donald E. Steiss, John M. Johnsen |
2000-05-09 |