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Home › Performance and power improvement on DMA writes to level two combined cache/SRAM that is cached in level one data cache and line is valid and dirty

Performance and power improvement on DMA writes to level two combined cache/SRAM that is cached in level one data cache and line is valid and dirty

US Patent 9298643 · Granted Mar 29, 2016

Estimated economic value: $25,607,000 ⓘ

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