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Home › Performance and power improvement on DMA writes to level two combined cache/SRAM that is caused in level one data cache and line is valid and dirty

Performance and power improvement on DMA writes to level two combined cache/SRAM that is caused in level one data cache and line is valid and dirty

US Patent 9075744 · Granted Jul 7, 2015

Estimated economic value: $9,588,000 ⓘ

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