Issued Patents All Time
Showing 76–100 of 119 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10747636 | Streaming engine with deferred exception reporting | Joseph Zbiciak, Timothy David Anderson, Duc Quang Bui | 2020-08-18 |
| 10732945 | Nested loop control | Timothy David Anderson, Todd T. Hahn, Alan L. Davis | 2020-08-04 |
| 10606596 | Cache preload operations using streaming engine | Joseph Zbiciak, Timothy David Anderson, Jonathan (Son) Hung Tran, Daniel Wu, Abhijeet Ashok Chachad +1 more | 2020-03-31 |
| 10599433 | Cache management operations using streaming engine | Joseph Zbiciak, Timothy David Anderson, Jonathan (Son) Hung Tran, Daniel Wu, Abhijeet Ashok Chachad +1 more | 2020-03-24 |
| 10560428 | Flexible hybrid firewall architecture | Amritpal Singh Mundra, Brian J. Karguth, Timothy David Anderson, Charles Fuoco | 2020-02-11 |
| 10394718 | Slot/sub-slot prefetch architecture for multiple memory requestors | Joseph Zbiciak, Matthew D. Pierson | 2019-08-27 |
| 10311007 | Multicore bus architecture with non-blocking high performance transaction credit system | David Matthew Thompson, Timothy David Anderson, Joseph Zbiciak, Abhijeet Ashok Chachad, Matthew D. Pierson | 2019-06-04 |
| 10162641 | Highly integrated scalable, flexible DSP megamodule architecture | Timothy David Anderson, Joseph Zbiciak, Duc Quang Bui, Abhijeet Ashok Chachad, Naveen Bhoria +3 more | 2018-12-25 |
| 10061675 | Streaming engine with deferred exception reporting | Joseph Zbiciak, Timothy David Anderson, Duc Quang Bui | 2018-08-28 |
| 10037439 | Secure master and secure guest endpoint security firewall | Timothy David Anderson, Joseph Zbiciak, Matthew D. Pierson | 2018-07-31 |
| 9904645 | Multicore bus architecture with non-blocking high performance transaction credit system | David Matthew Thompson, Timothy David Anderson, Joseph Zbiciak, Abhijeet Ashok Chachad, Matthew D. Pierson | 2018-02-27 |
| 9898415 | Slot/sub-slot prefetch architecture for multiple memory requestors | Joseph Zbiciak, Matthew D. Pierson | 2018-02-20 |
| 9652404 | Multicore, multibank, fully concurrent coherence controller | Matthew D. Pierson | 2017-05-16 |
| 9606803 | Highly integrated scalable, flexible DSP megamodule architecture | Timothy David Anderson, Joseph Zbiciak, Duc Quang Bui, Abhijeet Ashok Chachad, Naveen Bhoria +3 more | 2017-03-28 |
| 9557936 | Protection of memories, datapath and pipeline registers, and other storage elements by distributed delayed detection and correction of soft errors | Timothy David Anderson, Joseph Zbiciak, Abhijeet Ashok Chachad, Naveen Bhoria, David Matthew Thompson +2 more | 2017-01-31 |
| 9489314 | Multi-master cache coherent speculation aware memory controller with advanced arbitration, virtualization and EDC | Matthew D. Pierson, Timothy David Anderson | 2016-11-08 |
| 9465742 | Synchronizing barrier support with zero performance impact | Daniel Wu | 2016-10-11 |
| 9465767 | Multi-processor, multi-domain, multi-protocol cache coherent speculation aware shared memory controller and interconnect | Matthew D. Pierson, Daniel Wu, Timothy David Anderson | 2016-10-11 |
| 9465741 | Multi processor multi domain conversion bridge with out of order return buffering | Daniel Wu, Matthew D. Pierson, Timothy David Anderson | 2016-10-11 |
| 9448767 | Three-term predictive adder and/or subtracter | Timothy David Anderson, Mujibur Rahman | 2016-09-20 |
| 9424193 | Flexible arbitration scheme for multi endpoint atomic accesses in multicore systems | Matthew D. Pierson | 2016-08-23 |
| 9372796 | Optimum cache access scheme for multi endpoint atomic access in a multicore system | Matthew D. Pierson | 2016-06-21 |
| 9372799 | Coherent cache system with optional acknowledgement for out-of-order coherence transaction completion | Daniel Wu, Matthew D. Pierson, Timothy David Anderson | 2016-06-21 |
| 9372808 | Deadlock-avoiding coherent system on chip interconnect | Matthew D. Pierson, Daniel Wu | 2016-06-21 |
| 9304954 | Multi processor bridge with mixed Endian mode support | Daniel Wu, Matthew D. Pierson | 2016-04-05 |