Issued Patents All Time
Showing 51–75 of 294 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12086074 | Method and apparatus for permuting streamed data elements | Soujanya Narnur, Mujibur Rahman, Duc Quang Bui | 2024-09-10 |
| 12086064 | Aliased mode for cache controller | Abhijeet Ashok Chachad, Pramod Kumar Swami, Naveen Bhoria, David Matthew Thompson, Neelima Muralidharan | 2024-09-10 |
| 12072824 | Multicore bus architecture with non-blocking high performance transaction credit system | David Matthew Thompson, Joseph Zbiciak, Abhijeet Ashok Chachad, Kai Chirca, Matthew D. Pierson | 2024-08-27 |
| 12072814 | Methods and apparatus to facilitate read-modify-write support in a victim cache | Naveen Bhoria, Pete Michael Hippleheuser | 2024-08-27 |
| 12072812 | Highly integrated scalable, flexible DSP megamodule architecture | Joseph Zbiciak, Duc Quang Bui, Abhijeet Ashok Chachad, Kai Chirca, Naveen Bhoria +3 more | 2024-08-27 |
| 12067396 | Variable latency instructions | — | 2024-08-20 |
| 12061908 | Dual data streams sharing dual level two cache access ports to maximize bandwidth utilization | Joseph Zbiciak | 2024-08-13 |
| 12050914 | Cache management operations using streaming engine | Joseph Zbiciak, Jonathan (Son) Hung Tran, Kai Chirca, Daniel Wu, Abhijeet Ashok Chachad +1 more | 2024-07-30 |
| 12045617 | Two-dimensional zero padding in a stream of matrix elements | William Franklin Leven, Asheesh Bhardwaj, Son Hung Tran | 2024-07-23 |
| 12045172 | Method and apparatus for implied bit handling in floating point multiplication | Mujibur Rahman | 2024-07-23 |
| 12032961 | Vector maximum and minimum with indexing | Duc Quang Bui, Peter Richard Dent | 2024-07-09 |
| 12032490 | Method and apparatus for vector sorting | Mujibur Rahman | 2024-07-09 |
| 12019559 | Method and apparatus for dual issue multiply instructions | Mujibur Rahman | 2024-06-25 |
| 12007907 | Victim cache with write miss merging | Naveen Bhoria, Pete Michael Hippleheuser | 2024-06-11 |
| 12007904 | Method and apparatus for vector based matrix multiplication | Asheesh Bhardwaj, Mujibur Rahman | 2024-06-11 |
| 12001345 | Victim cache that supports draining write-miss entries | Naveen Bhoria, Pete Michael Hippleheuser | 2024-06-04 |
| 12001282 | Write control for read-modify-write operations in cache memory | Abhijeet Ashok Chachad, David Matthew Thompson, Daniel Wu | 2024-06-04 |
| 11994949 | Streaming engine with error detection, correction and restart | Joseph Zbiciak | 2024-05-28 |
| 11989072 | Controlling the number of powered vector lanes via a register field | Duc Quang Bui | 2024-05-21 |
| 11983559 | Streaming engine with short cut start instructions | Joseph Zbiciak | 2024-05-14 |
| 11977887 | System and method to control the number of active vector lanes in a processor | Duc Quang Bui | 2024-05-07 |
| 11972236 | Nested loop control | Kai Chirca, Todd T. Hahn, Alan L. Davis | 2024-04-30 |
| 11960892 | Conditional execution specification of instructions using conditional extension slots in the same execute packet in a VLIW processor | Duc Quang Bui, Joseph Zbiciak | 2024-04-16 |
| 11960567 | Implementing fundamental computational primitives using a matrix multiplication accelerator (MMA) | Arthur John Redfern, Kai Chirca, Chenchi Luo, Zhenhua Yu | 2024-04-16 |
| 11940930 | Methods and apparatus to facilitate atomic operations in victim cache | Naveen Bhoria, Pete Michael Hippleheuser | 2024-03-26 |