Issued Patents All Time
Showing 101–125 of 294 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11755203 | Multicore shared cache operation engine | Kai Chirca, Matthew D. Pierson, David E. Smith | 2023-09-12 |
| 11741020 | Methods and apparatus to facilitate fully pipelined read-modify-write support in level 1 data cache using store queue and data forwarding | Naveen Bhoria, Pete Michael Hippleheuser | 2023-08-29 |
| 11734194 | Method and apparatus for dual issue multiply instructions | Mujibur Rahman | 2023-08-22 |
| 11714760 | Methods and apparatus to reduce bank pressure using aggressive write merging | Naveen Bhoria, Pete Michael Hippleheuser | 2023-08-01 |
| 11709778 | Streaming engine with early and late address and loop count registers to track architectural state | Joseph Zbiciak | 2023-07-25 |
| 11704046 | Quick clearing of registers | Duc Quang Bui, Soujanya Narnur | 2023-07-18 |
| 11693791 | Victim cache that supports draining write-miss entries | Naveen Bhoria, Pete Michael Hippleheuser | 2023-07-04 |
| 11693790 | Methods and apparatus to facilitate write miss caching in cache system | Naveen Bhoria, Pete Michael Hippleheuser | 2023-07-04 |
| 11693661 | Mechanism for interrupting and resuming execution on an unprotected pipeline processor | Joseph Zbiciak, Kai Chirca | 2023-07-04 |
| 11681532 | Method for forming constant extensions in the same execute packet in a VLIW processor | Duc Quang Bui, Joseph Zbiciak | 2023-06-20 |
| 11681526 | Method and apparatus for vector based finite impulse response (FIR) filtering | Mujibur Rahman, Asheesh Bhardwaj | 2023-06-20 |
| 11675700 | Cache coherence shared state suppression | Abhijeet Ashok Chachad, David Matthew Thompson, Kai Chirca | 2023-06-13 |
| 11669463 | Method and apparatus for permuting streamed data elements | Soujanya Narnur, Mujibur Rahman, Duc Quang Bui | 2023-06-06 |
| 11640357 | Methods and apparatus to facilitate read-modify-write support in a victim cache | Naveen Bhoria, Pete Michael Hippleheuser | 2023-05-02 |
| 11636040 | Methods and apparatus for inflight data forwarding and invalidation of pending writes in store queue | Naveen Bhoria, Pete Michael Hippleheuser | 2023-04-25 |
| 11620230 | Methods and apparatus to facilitate read-modify-write support in a coherent victim cache with parallel data paths | Naveen Bhoria, Pete Michael Hippleheuser | 2023-04-04 |
| 11614940 | Vector maximum and minimum with indexing | Duc Quang Bui, Peter Richard Dent | 2023-03-28 |
| 11609862 | Method and apparatus to sort a vector for a bitonic sorting algorithm | Mujibur Rahman | 2023-03-21 |
| 11604652 | Streaming address generation | Duc Quang Bui, Joseph Zbiciak, Sahithi KRISHNA, Soujanya Narnur | 2023-03-14 |
| 11580024 | Memory pipeline control in a hierarchical memory system | Abhijeet Ashok Chachad, Kai Chirca, David Matthew Thompson | 2023-02-14 |
| 11573847 | Streaming engine with deferred exception reporting | Joseph Zbiciak, Duc Quang Bui, Kai Chirca | 2023-02-07 |
| 11556338 | Vector SIMD VLIW data path architecture | Duc Quang Bui, Mujibur Rahman, Joseph Zbiciak, Eric Biscondi, Peter Richard Dent +2 more | 2023-01-17 |
| 11550573 | System and method to control the number of active vector lanes in a processor | Duc Quang Bui | 2023-01-10 |
| 11550575 | Method and apparatus for vector sorting | Mujibur Rahman | 2023-01-10 |
| 11507513 | Methods and apparatus to facilitate an atomic operation and/or a histogram operation in cache pipeline | Naveen Bhoria, Pete Michael Hippleheuser | 2022-11-22 |