Issued Patents All Time
Showing 76–100 of 294 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11940929 | Methods and apparatus to reduce read-modify-write cycles for non-aligned writes | Naveen Bhoria, Pete Michael Hippleheuser | 2024-03-26 |
| 11940918 | Memory pipeline control in a hierarchical memory system | Abhijeet Ashok Chachad, Kai Chirca, David Matthew Thompson | 2024-03-26 |
| 11922166 | Vector SIMD VLIW data path architecture | Duc Quang Bui, Mujibur Rahman, Joseph Zbiciak, Eric Biscondi, Peter Richard Dent +2 more | 2024-03-05 |
| 11921643 | Method and apparatus for dual multiplication units in a data path | Mujibur Rahman, Soujanya Narnur | 2024-03-05 |
| 11921637 | Write streaming with cache write acknowledgment in a processor | Abhijeet Ashok Chachad, David Matthew Thompson | 2024-03-05 |
| 11907753 | Controller with caching and non-caching modes | Abhijeet Ashok Chachad, David Matthew Thompson | 2024-02-20 |
| 11907721 | Inserting predefined pad values into a stream of vectors | Asheesh Bhardwaj, Son Hung Tran | 2024-02-20 |
| 11900117 | Mechanism to queue multiple streams to run on streaming engine | Jonathan (Son) Hung Tran, Joseph Zbiciak | 2024-02-13 |
| 11900112 | Vector reverse | Duc Quang Bui | 2024-02-13 |
| 11886353 | Hybrid victim cache and write miss buffer with fence operation | Naveen Bhoria, Pete Michael Hippleheuser | 2024-01-30 |
| 11868272 | Methods and apparatus for allocation in a victim cache system | Naveen Bhoria, Pete Michael Hippleheuser | 2024-01-09 |
| 11853225 | Software-hardware memory management modes | Joseph Zbiciak, Kai Chirca, Daniel Wu | 2023-12-26 |
| 11836494 | System and method for addressing data in memory | Duc Quang Bui, Joseph Zbiciak, Kai Chirca | 2023-12-05 |
| 11829300 | Method and apparatus for vector sorting using vector permutation logic | Mujibur Rahman | 2023-11-28 |
| 11822786 | Delayed snoop for improved multi-process false sharing parallel thread performance | Kai Chirca | 2023-11-21 |
| 11816485 | Nested loop control | Kai Chirca, Todd T. Hahn, Alan L. Davis | 2023-11-14 |
| 11804858 | Butterfly network on load data return | Dheera Balasubramanian, Joseph Zbiciak, Duc Quang Bui | 2023-10-31 |
| 11803505 | Multicore bus architecture with wire reduction and physical congestion minimization via shared transaction channels | David Matthew Thompson, Joseph Zbiciak, Abhijeet Ashok Chachad, Kai Chirca, Matthew D. Pierson | 2023-10-31 |
| 11803486 | Write merging on stores with different privilege levels | Naveen Bhoria, Pete Michael Hippleheuser | 2023-10-31 |
| 11789742 | Pipeline protection for CPUs with save and restore of intermediate results | Duc Quang Bui, Joseph Zbiciak, Reid E. Tatge | 2023-10-17 |
| 11782718 | Implied fence on stream open | Naveen Bhoria, Kai Chirca, Duc Quang Bui, Abhijeet Ashok Chachad, Son Hung Tran | 2023-10-10 |
| 11775446 | Methods and apparatus to facilitate atomic compare and swap in cache for a coherent level 1 data cache system | Naveen Bhoria, Pete Michael Hippleheuser | 2023-10-03 |
| 11768685 | Processing device with vector transformation execution | Mujibur Rahman, Joseph Zbiciak | 2023-09-26 |
| 11762780 | Write merging on stores with different tags | Naveen Bhoria, Pete Michael Hippleheuser | 2023-09-19 |
| 11755322 | Vector load and duplicate operations | Duc Quang Bui, Peter Richard Dent | 2023-09-12 |