Issued Patents All Time
Showing 26–50 of 294 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12223165 | Multicore, multibank, fully concurrent coherence controller | Matthew D. Pierson, Kai Chirca | 2025-02-11 |
| 12223327 | CPUs with capture queues to save and restore intermediate results and out-of-order results | Duc Quang Bui, Joseph Zbiciak, Reid E. Tatge | 2025-02-11 |
| 12217054 | Method of storing register data elements to interleave with data elements of a different register, a processor thereof, and a system thereof | Duc Quang Bui, Alan L. Davis, Dheera Balasubramanian Samudrala | 2025-02-04 |
| 12216591 | Atomic compare and swap in a coherent cache system | Naveen Bhoria, Pete Michael Hippleheuser | 2025-02-04 |
| 12210463 | Aggressive write flush scheme for a victim cache | Naveen Bhoria, Pete Michael Hippleheuser | 2025-01-28 |
| 12204905 | Inserting predefined pad values into a stream of vectors | Asheesh Bhardwaj, Son Hung Tran | 2025-01-21 |
| 12197347 | Methods and apparatus to reduce bank pressure using aggressive write merging | Naveen Bhoria, Pete Michael Hippleheuser | 2025-01-14 |
| 12197917 | Exit history based branch prediction | Kai Chirca, David E. Smith, Paul Daniel Gauvreau | 2025-01-14 |
| 12197332 | Memory pipeline control in a hierarchical memory system | Abhijeet Ashok Chachad, Kai Chirca, David Matthew Thompson | 2025-01-14 |
| 12189540 | Fully pipelined read-modify-write support | Naveen Bhoria, Pete Michael Hippleheuser | 2025-01-07 |
| 12182038 | Methods and apparatus for allocation in a victim cache system | Naveen Bhoria, Pete Michael Hippleheuser | 2024-12-31 |
| 12182573 | Processing device with vector transformation execution | Mujibur Rahman, Joseph Zbiciak | 2024-12-31 |
| 12175244 | Nested loop control | Kai Chirca, Todd T. Hahn, Alan L. Davis | 2024-12-24 |
| 12159030 | Multicore shared cache operation engine | Kai Chirca, Matthew D. Pierson, David E. Smith | 2024-12-03 |
| 12147353 | Methods and apparatus for read-modify-write support in multi-banked data RAM cache for bank arbitration | Naveen Bhoria, Pete Michael Hippleheuser | 2024-11-19 |
| 12141079 | Atomic operations and histogram operations in a cache pipeline | Naveen Bhoria, Pete Michael Hippleheuser | 2024-11-12 |
| 12141078 | Victim cache with dynamic allocation of entries | Naveen Bhoria, Pete Michael Hippleheuser | 2024-11-12 |
| 12141073 | Methods and apparatus for inflight data forwarding and invalidation of pending writes in store queue | Naveen Bhoria, Pete Michael Hippleheuser | 2024-11-12 |
| 12135646 | Cache coherence shared state suppression | Abhijeet Ashok Chachad, David Matthew Thompson, Kai Chirca | 2024-11-05 |
| 12124728 | Quick clearing of registers | Duc Quang Bui, Soujanya Narnur | 2024-10-22 |
| 12118358 | One-dimensional zero padding in a stream of matrix elements | Son Hung Tran, Shyam Jagannathan | 2024-10-15 |
| 12105635 | Method and apparatus for vector permutation | Mujibur Rahman, Dheera Balasubramanian Samudrala, Peter Richard Dent, Duc Quang Bui | 2024-10-01 |
| 12105640 | Methods and apparatus for eviction in dual datapath victim cache system | Naveen Bhoria, Pete Michael Hippleheuser | 2024-10-01 |
| 12099843 | Streaming address generation | Duc Quang Bui, Joseph Zbiciak, Sahithi KRISHNA, Soujanya Narnur | 2024-09-24 |
| 12099400 | Streaming engine with deferred exception reporting | Joseph Zbiciak, Duc Quang Bui, Kai Chirca | 2024-09-24 |