Issued Patents All Time
Showing 151–175 of 294 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11334494 | Write merging on stores with different tags | Naveen Bhoria, Pete Michael Hippleheuser | 2022-05-17 |
| 11327761 | Processing device with vector transformation execution | Mujibur Rahman, Joseph Zbiciak | 2022-05-10 |
| 11321268 | Multicore bus architecture with wire reduction and physical congestion minimization via shared transaction channels | David Matthew Thompson, Joseph Zbiciak, Abhijeet Ashok Chachad, Kai Chirca, Matthew D. Pierson | 2022-05-03 |
| 11307791 | Quick clearing of registers | Duc Quang Bui, Soujanya Narnur | 2022-04-19 |
| 11307858 | Cache preload operations using streaming engine | Joseph Zbiciak, Jonathan (Son) Hung Tran, Kai Chirca, Daniel Wu, Abhijeet Ashok Chachad +1 more | 2022-04-19 |
| 11301248 | Method and apparatus for dual multiplication units in a data path | Mujibur Rahman, Soujanya Narnur | 2022-04-12 |
| 11294826 | Method and apparatus for vector permutation | Mujibur Rahman, Dheera Balasubramanian Samudrala, Peter Richard Dent, Duc Quang Bui | 2022-04-05 |
| 11294673 | Method and apparatus for dual issue multiply instructions | Mujibur Rahman | 2022-04-05 |
| 11288067 | Vector reverse | Duc Quang Bui | 2022-03-29 |
| 11281464 | Method and apparatus to sort a vector for a bitonic sorting algorithm | Mujibur Rahman | 2022-03-22 |
| 11275692 | Methods and apparatus for multi-banked victim cache with dual datapath | Naveen Bhoria, Pete Michael Hippleheuser | 2022-03-15 |
| 11269650 | Pipeline protection for CPUs with save and restore of intermediate results | Duc Quang Bui, Joseph Zbiciak, Reid E. Tatge | 2022-03-08 |
| 11269774 | Delayed snoop for improved multi-process false sharing parallel thread performance | Kai Chirca | 2022-03-08 |
| 11256508 | Inserting null vectors into a stream of vectors | Asheesh Bhardwaj, William Franklin Leven, Son Hung Tran | 2022-02-22 |
| 11249759 | Two-dimensional zero padding in a stream of matrix elements | William Franklin Leven, Asheesh Bhardwaj, Son Hung Tran | 2022-02-15 |
| 11243883 | Cache coherence shared state suppression | Abhijeet Ashok Chachad, David Matthew Thompson, Kai Chirca | 2022-02-08 |
| 11237968 | Multicore shared cache operation engine | Kai Chirca, Matthew D. Pierson, David E. Smith | 2022-02-01 |
| 11237831 | Method and apparatus for permuting streamed data elements | Soujanya Narnur, Mujibur Rahman, Duc Quang Bui | 2022-02-01 |
| 11231929 | One-dimensional zero padding in a stream of matrix elements | Son Hung Tran, Shyam Jagannathan | 2022-01-25 |
| 11212256 | Flexible hybrid firewall architecture | Amritpal Singh Mundra, Brian J. Karguth, Kai Chirca, Charles Fuoco | 2021-12-28 |
| 11210098 | Variable latency instructions | — | 2021-12-28 |
| 11194729 | Victim cache that supports draining write-miss entries | Naveen Bhoria, Pete Michael Hippleheuser | 2021-12-07 |
| 11182200 | Streaming engine with short cut start instructions | Joseph Zbiciak | 2021-11-23 |
| 11138117 | Memory pipeline control in a hierarchical memory system | Abhijeet Ashok Chachad, Kai Chirca, David Matthew Thompson | 2021-10-05 |
| 11119779 | Dual data streams sharing dual level two cache access ports to maximize bandwidth utilization | Joseph Zbiciak | 2021-09-14 |