Issued Patents All Time
Showing 176–200 of 294 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11119935 | Methods and apparatus to facilitate atomic compare and swap in cache for a coherent level 1 data cache system | Naveen Bhoria, Pete Michael Hippleheuser | 2021-09-14 |
| 11119776 | Cache management operations using streaming engine | Joseph Zbiciak, Jonathan (Son) Hung Tran, Kai Chirca, Daniel Wu, Abhijeet Ashok Chachad +1 more | 2021-09-14 |
| 11113062 | Inserting predefined pad values into a stream of vectors | Asheesh Bhardwaj, Son Hung Tran | 2021-09-07 |
| 11106463 | System and method for addressing data in memory | Duc Quang Bui, Joseph Zbiciak, Kai Chirca | 2021-08-31 |
| 11106462 | Method and apparatus for vector sorting | Mujibur Rahman | 2021-08-31 |
| 11099933 | Streaming engine with error detection, correction and restart | Joseph Zbiciak | 2021-08-24 |
| 11101825 | Butterfly network on load data return | Dheera Balasubramanian, Joseph Zbiciak, Due Quang Bui | 2021-08-24 |
| 11086967 | Implementing fundamental computational primitives using a matrix multiplication accelerator (MMA) | Arthur John Redfern, Kai Chirca, Chenchi Luo, Zhenhua Yu | 2021-08-10 |
| 11086778 | Multicore shared cache operation engine | Kai Chirca, Joseph Zbiciak, David E. Smith, Matthew D. Pierson | 2021-08-10 |
| 11080047 | Register file structures combining vector and scalar data with global and local accesses | Due Quang Bui, Mel Alan Phipps, Todd T. Hahn, Joseph Zbiciak | 2021-08-03 |
| 11055095 | Nested loop control | Kai Chirca, Todd T. Hahn, Alan L. Davis | 2021-07-06 |
| 11048513 | Entering protected pipeline mode with clearing | Joseph Zbiciak, Duc Quang Bui, Mel Alan Phipps, Todd T. Hahn | 2021-06-29 |
| 11036648 | Highly integrated scalable, flexible DSP megamodule architecture | Joseph Zbiciak, Duc Quang Bui, Abhijeet Ashok Chachad, Kai Chirca, Naveen Bhoria +3 more | 2021-06-15 |
| 11029997 | Entering protected pipeline mode without annulling pending instructions | Duc Quang Bui | 2021-06-08 |
| 10990398 | Mechanism for interrupting and resuming execution on an unprotected pipeline processor | Joseph Zbiciak, Kai Chirca | 2021-04-27 |
| 10963254 | Mechanism to queue multiple streams to run on streaming engine | Jonathan (Son) Hung Tran, Joseph Zbiciak | 2021-03-30 |
| 10963255 | Implied fence on stream open | Naveen Bhoria, Kai Chirca, Duc Quang Bui, Abhijeet Ashok Chachad, Son Hung Tran | 2021-03-30 |
| 10963252 | Vector maximum and minimum with indexing | Duc Quang Bui, Peter Richard Dent | 2021-03-30 |
| 10936317 | Streaming address generation | Duc Quang Bui, Joseph Zbiciak, Sahithi KRISHNA, Soujanya Narnur | 2021-03-02 |
| 10871965 | System and method to control the number of active vector lanes in a processor | Duc Quang Bui | 2020-12-22 |
| 10817587 | Reconfigurable matrix multiplier system and method | Arthur John Redfern, Donald E. Steiss, Kai Chirca | 2020-10-27 |
| 10795844 | Multicore bus architecture with non-blocking high performance transaction credit system | David Matthew Thompson, Joseph Zbiciak, Abhijeet Ashok Chachad, Kai Chirca, Matthew D. Pierson | 2020-10-06 |
| 10768933 | Streaming engine with stream metadata saving for context switching | Joseph Zbiciak | 2020-09-08 |
| 10747636 | Streaming engine with deferred exception reporting | Joseph Zbiciak, Duc Quang Bui, Kai Chirca | 2020-08-18 |
| 10732689 | Controlling the number of powered vector lanes via a register field | Duc Quang Bui | 2020-08-04 |