Issued Patents All Time
Showing 226–250 of 294 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10007518 | Register file structures combining vector and scalar data with global and local accesses | Duc Quang Bui, Mel Alan Phipps, Todd T. Hahn, Joseph Zbiciak | 2018-06-26 |
| 9904645 | Multicore bus architecture with non-blocking high performance transaction credit system | David Matthew Thompson, Joseph Zbiciak, Abhijeet Ashok Chachad, Kai Chirca, Matthew D. Pierson | 2018-02-27 |
| 9788011 | Faster and more efficient different precision sum of absolute differences for dynamically configurable block searches for motion estimation | Mujibur Rahman, Djordje Senicic | 2017-10-10 |
| 9675185 | Refrigerated merchandiser with shelf air discharge | Ken Nguyen | 2017-06-13 |
| 9606803 | Highly integrated scalable, flexible DSP megamodule architecture | Joseph Zbiciak, Duc Quang Bui, Abhijeet Ashok Chachad, Kai Chirca, Naveen Bhoria +3 more | 2017-03-28 |
| 9582273 | Faster and more efficient different precision sum of absolute differences for dynamically configurable block searches for motion estimation | Mujibur Rahman, Djordje Senicic | 2017-02-28 |
| 9557936 | Protection of memories, datapath and pipeline registers, and other storage elements by distributed delayed detection and correction of soft errors | Joseph Zbiciak, Abhijeet Ashok Chachad, Kai Chirca, Naveen Bhoria, David Matthew Thompson +2 more | 2017-01-31 |
| 9489314 | Multi-master cache coherent speculation aware memory controller with advanced arbitration, virtualization and EDC | Kai Chirca, Matthew D. Pierson | 2016-11-08 |
| 9489307 | Multi domain bridge with auto snoop response | Daniel Wu | 2016-11-08 |
| 9489197 | Highly efficient different precision complex multiply accumulate to enhance chip rate functionality in DSSS cellular systems | Mujibur Rahman, Peter Richard Dent, Duc Quang Bui | 2016-11-08 |
| RE46193 | Distributed power control for controlling power consumption based on detected activity of logic blocks | Lewis Nardini, Jose Luis Flores, Abhijeet Ashok Chachad, Raguram Damodaran, Joseph Zbiciak +1 more | 2016-11-01 |
| 9465741 | Multi processor multi domain conversion bridge with out of order return buffering | Kai Chirca, Daniel Wu, Matthew D. Pierson | 2016-10-11 |
| 9462896 | Door for a refrigerated merchandiser | Craig S. Reichert | 2016-10-11 |
| 9465767 | Multi-processor, multi-domain, multi-protocol cache coherent speculation aware shared memory controller and interconnect | Kai Chirca, Matthew D. Pierson, Daniel Wu | 2016-10-11 |
| 9456706 | Merchandiser with airflow divider | Ken Nguyen | 2016-10-04 |
| 9448767 | Three-term predictive adder and/or subtracter | Mujibur Rahman, Kai Chirca | 2016-09-20 |
| 9372799 | Coherent cache system with optional acknowledgement for out-of-order coherence transaction completion | Daniel Wu, Matthew D. Pierson, Kai Chirca | 2016-06-21 |
| 9289079 | Door for a refrigerated merchandiser | Craig S. Reichert | 2016-03-22 |
| 9267635 | Pipeline liner monitoring system | Mohan Gopalkrishna Kulkarni | 2016-02-23 |
| 9239735 | Compiler-control method for load speculation in a statically scheduled microprocessor | Joseph Zbiciak, Duc Quang Bui, Mel Alan Phipps, Todd T. Hahn | 2016-01-19 |
| 9239798 | Prefetcher with arbitrary downstream prefetch cancelation | Matthew D. Pierson, Joseph Zbiciak, Kai Chirca, Amitabh Menon | 2016-01-19 |
| 9220354 | Merchandiser with airflow divider | Ken Nguyen | 2015-12-29 |
| 9208120 | Multi-processor, multi-domain, multi-protocol cache coherent speculation aware shared memory controller and interconnect | Kai Chirca, Matthew D. Pierson, Daniel Wu | 2015-12-08 |
| 9189456 | Technique for optimization and re-use of hardware in the implementation of instructions used in Viterbi and turbo decoding, using carry save arithmetic | Shriram D. Moharil | 2015-11-17 |
| 9152586 | Coherent cache system with optional acknowledgement for out-of-order coherence transaction completion | Daniel Wu, Matthew D. Pierson, Kai Chirca | 2015-10-06 |