Issued Patents All Time
Showing 276–294 of 294 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8117422 | Fast address translation for linear and circular modes | Kai Chirca | 2012-02-14 |
| 7502727 | Tracing user change of program counter during stop event | Manisha Agarwala, Lewis Nardini | 2009-03-10 |
| 7325178 | Programmable built in self test of memory | Raguram Damodaran, Sanjive Agarwala, Joel J. Graber | 2008-01-29 |
| 7240277 | Memory error detection reporting | David Quintin Bell, Abhijeet Ashok Chachad, Peter Richard Dent, Raguram Damodaran | 2007-07-03 |
| 6981178 | Separation of debug windows by IDS bit | Lewis Nardini, Gary L. Swoboda | 2005-12-27 |
| 6963965 | Instruction-programmable processor with instruction loop cache | — | 2005-11-08 |
| 6834338 | Microprocessor with branch-decrement instruction that provides a target and conditionally modifies a test register if the register meets a condition | David Hoyle | 2004-12-21 |
| 6665767 | Programmer initiated cache block operations | David A. Comisky, Sanjive Agarwala, Charles Fuoco | 2003-12-16 |
| 6606686 | Unified memory system architecture including cache and directly addressable static random access memory | Sanjive Agarwala, Charles Fuoco, David A. Comisky, Christopher L. Mobley | 2003-08-12 |
| 6594711 | Method and apparatus for operating one or more caches in conjunction with direct memory access controller | Sanjive Agarwala, Charles Fuoco, David A. Comisky | 2003-07-15 |
| 6539467 | Microprocessor with non-aligned memory access | David Hoyle, Donald E. Steiss, Steven D. Krueger | 2003-03-25 |
| 6535958 | Multilevel cache system coherence with memory selectively configured as cache or direct access memory and direct memory access | Charles Fuoco, Sanjive Agarwala, David A. Comisky, Christopher L. Mobley | 2003-03-18 |
| 6484237 | Unified multilevel memory system architecture which supports both cache and addressable SRAM | Sanjive Agarwala, Charles Fuoco, David A. Comisky | 2002-11-19 |
| 6446241 | Automated method for testing cache | Christopher L. Mobley, Charles Fuoco, Sanjive Agarwala | 2002-09-03 |
| 6170053 | Microprocessor with circuits, systems and methods for responding to branch instructions based on history of prediction accuracy | Simonjit Dutta, Jonathan H. Shiell | 2001-01-02 |
| 6009516 | Pipelined microprocessor with efficient self-modifying code detection and handling | Donald E. Steiss, Sanjive Agarwala | 1999-12-28 |
| 5983370 | Four state token passing alignment fault state circuit for microprocessor address misalignment fault generation having combined read/write port | — | 1999-11-09 |
| 5951679 | Microprocessor circuits, systems, and methods for issuing successive iterations of a short backward branch loop in a single cycle | Jonathan H. Shiell | 1999-09-14 |
| 5895497 | Microprocessor with pipelining, memory size evaluation, micro-op code and tags | — | 1999-04-20 |