Issued Patents All Time
Showing 251–275 of 294 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9129071 | Coherence controller slot architecture allowing zero latency write commit | Matthew D. Pierson, Kai Chirca | 2015-09-08 |
| 9080798 | Control method for modular refrigerated merchandiser | Doron Shapiro | 2015-07-14 |
| 9009414 | Prefetch address hit prediction to reduce memory access latency | Joseph Zbiciak, Matthew D. Pierson | 2015-04-14 |
| 8977819 | Prefetch stream filter with FIFO allocation and stream direction prediction | Kai Chirca, Joseph Zbiciak, Matthew D. Pierson | 2015-03-10 |
| 8918445 | Circuit which performs split precision, signed/unsigned, fixed and floating point, real and complex multiplication | Mujibur Rahman | 2014-12-23 |
| 8904115 | Cache with multiple access pipelines | Abhijeet Ashok Chachad, Raguram Damodaran, Jonathan (Son) Hung Tran, Sanjive Agarwala | 2014-12-02 |
| 8880855 | Dual register data path architecture with registers in a data file divided into groups and sub-groups | Duc Quang Bui, Eric Biscondi, Shriram D. Moharil, Mujibur Rahman, Soujanya Narnur +2 more | 2014-11-04 |
| 8858013 | Low heat transfer magnetic shelf attachment | Joel Attey, Mark A. Miller, Ken Nguyen | 2014-10-14 |
| 8832166 | Floating point multiplier circuit with optimized rounding calculation | — | 2014-09-09 |
| 8806110 | Flexible memory protection and translation unit | Joseph Zbiciak, Amitabh Menon | 2014-08-12 |
| 8805903 | Extended-width shifter for arithmetic logic unit | Shriram D. Moharil | 2014-08-12 |
| 8732551 | Memory controller with automatic error detection and correction | Kai Chirca, Amitabh Menon | 2014-05-20 |
| 8732370 | Multilayer arbitration for access to multiple destinations | Kai Chirca, Amitabh Menon | 2014-05-20 |
| 8713086 | Three-term predictive adder and/or subtracter | Mujibur Rahman, Kai Chirca | 2014-04-29 |
| 8706940 | High fairness variable priority arbitration method | Kai Chirca | 2014-04-22 |
| 8706969 | Variable line size prefetcher for multiple memory requestors | Kai Chirca | 2014-04-22 |
| 8601040 | Reduced-level shift overflow detection | Shriram D. Moharil | 2013-12-03 |
| 8601221 | Speculation-aware memory controller arbiter | Kai Chirca, Joseph Zbiciak | 2013-12-03 |
| 8572154 | Reduced-level two's complement arithmetic unit | Duc Quang Bui | 2013-10-29 |
| 8554823 | Technique for optimization and re-use of hardware in the implementation of instructions used in viterbi and turbo decoding, using carry and save arithmetic | Shriram D. Moharil | 2013-10-08 |
| 8554824 | Efficient technique for optimal re-use of hardware in the implementation of instructions used in viterbi, turbo and LPDC decoders | Shriram D. Moharil | 2013-10-08 |
| 8525565 | Family of multiplexer/flip-flops with enhanced testability | Mujibur Rahman, Alan Hales | 2013-09-03 |
| 8473689 | Predictive sequential prefetching for data caching | Kai Chirca | 2013-06-25 |
| 8397112 | Test chain testability in a system for testing tri-state functionality | Mujibur Rahman, Alan Hales | 2013-03-12 |
| 8201004 | Entry/exit control to/from a low power state in a complex multi level memory system | Lewis Nardini, Jose Luis Flores, Abhijeet Ashok Chachad, Raguram Damodaran, Joseph Zbiciak +1 more | 2012-06-12 |