Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9189456 | Technique for optimization and re-use of hardware in the implementation of instructions used in Viterbi and turbo decoding, using carry save arithmetic | Timothy David Anderson | 2015-11-17 |
| 8880855 | Dual register data path architecture with registers in a data file divided into groups and sub-groups | Timothy David Anderson, Duc Quang Bui, Eric Biscondi, Mujibur Rahman, Soujanya Narnur +2 more | 2014-11-04 |
| 8805903 | Extended-width shifter for arithmetic logic unit | Timothy David Anderson | 2014-08-12 |
| 8650239 | Hardware implementation of a Galois field multiplier | Rejitha Nair | 2014-02-11 |
| 8601040 | Reduced-level shift overflow detection | Timothy David Anderson | 2013-12-03 |
| 8554823 | Technique for optimization and re-use of hardware in the implementation of instructions used in viterbi and turbo decoding, using carry and save arithmetic | Timothy David Anderson | 2013-10-08 |
| 8554824 | Efficient technique for optimal re-use of hardware in the implementation of instructions used in viterbi, turbo and LPDC decoders | Timothy David Anderson | 2013-10-08 |