Issued Patents All Time
Showing 201–225 of 294 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10732945 | Nested loop control | Kai Chirca, Todd T. Hahn, Alan L. Davis | 2020-08-04 |
| 10713174 | Streaming engine with early and late address and loop count registers to track architectural state | Joseph Zbiciak | 2020-07-14 |
| 10628156 | Vector SIMD VLIW data path architecture | Duc Quang Bui, Mujibur Rahman, Joseph Zbiciak, Eric Biscondi, Peter Richard Dent +2 more | 2020-04-21 |
| 10620957 | Method for forming constant extensions in the same execute packet in a VLIW processor | Duc Quang Bui, Joseph Zbiciak | 2020-04-14 |
| 10606596 | Cache preload operations using streaming engine | Joseph Zbiciak, Jonathan (Son) Hung Tran, Kai Chirca, Daniel Wu, Abhijeet Ashok Chachad +1 more | 2020-03-31 |
| 10606598 | Dual data streams sharing dual level two cache access ports to maximize bandwidth utilization | Joseph Zbiciak | 2020-03-31 |
| 10599433 | Cache management operations using streaming engine | Joseph Zbiciak, Jonathan (Son) Hung Tran, Kai Chirca, Daniel Wu, Abhijeet Ashok Chachad +1 more | 2020-03-24 |
| 10592339 | Streaming engine with error detection, correction and restart | Joseph Zbiciak | 2020-03-17 |
| 10560428 | Flexible hybrid firewall architecture | Amritpal Singh Mundra, Brian J. Karguth, Kai Chirca, Charles Fuoco | 2020-02-11 |
| 10530397 | Butterfly network on load data return | Dheera Balasubramanian, Joseph Zbiciak, Duc Quang Bui | 2020-01-07 |
| 10423413 | Vector load and duplicate operations | Duc Quang Bui, Peter Richard Dent | 2019-09-24 |
| 10402199 | Conditional execution specification of instructions using conditional extension slots in the same execute packet in a VLIW processor | Duc Quang Bui, Joseph Zbiciak | 2019-09-03 |
| 10400936 | Conduit system and method of use thereof | Venkat R. Krishnan, Neerav Verma, Astrid-Cecilie Alveid Haarseth, David A. Baker, Stefanie Lynn Asher | 2019-09-03 |
| 10318293 | Predication methods for vector processors | Duc Quang Bui, Joseph Zbiciak | 2019-06-11 |
| 10311007 | Multicore bus architecture with non-blocking high performance transaction credit system | David Matthew Thompson, Joseph Zbiciak, Abhijeet Ashok Chachad, Kai Chirca, Matthew D. Pierson | 2019-06-04 |
| 10203958 | Streaming engine with stream metadata saving for context switching | Joseph Zbiciak | 2019-02-12 |
| 10182667 | Merchandiser with airflow divider | Ken Nguyen | 2019-01-22 |
| 10175981 | Method to control the number of active vector lanes for power efficiency | Duc Quang Bui | 2019-01-08 |
| 10162641 | Highly integrated scalable, flexible DSP megamodule architecture | Joseph Zbiciak, Duc Quang Bui, Abhijeet Ashok Chachad, Kai Chirca, Naveen Bhoria +3 more | 2018-12-25 |
| 10145621 | Multi-zone circuiting for a plate-fin and continuous tube heat exchanger | Ken Nguyen, Paul R. Laurentius | 2018-12-04 |
| 10083035 | Dual data streams sharing dual level two cache access ports to maximize bandwidth utilization | Joseph Zbiciak | 2018-09-25 |
| 10078551 | Streaming engine with error detection, correction and restart | Joseph Zbiciak | 2018-09-18 |
| 10061675 | Streaming engine with deferred exception reporting | Joseph Zbiciak, Duc Quang Bui, Kai Chirca | 2018-08-28 |
| 10037439 | Secure master and secure guest endpoint security firewall | Joseph Zbiciak, Matthew D. Pierson, Kai Chirca | 2018-07-31 |
| 10028594 | Merchandiser with merged air discharge | Ken Nguyen, Paul R. Laurentius | 2018-07-24 |