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Resolving multi-core shared cache access conflicts |
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2017-08-08 |
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Preventing system snoop and cross-snoop conflicts |
Yen-Cheng Liu, Krishnakanth V. Sistla, Jeffrey D. Gilbert |
2010-03-30 |
| 7353338 |
Credit mechanism for multiple banks of shared cache |
Yen-Cheng Liu, Krishnakanth V. Sistla, Ganapati Srinivasa, Geeyarpuram N. Santhanakrishnan |
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| 6216219 |
Microprocessor circuits, systems, and methods implementing a load target buffer with entries relating to prefetch desirability |
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2001-04-10 |
| 6108775 |
Dynamically loadable pattern history tables in a multi-task microprocessor |
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2000-08-22 |
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Data prefetching of a load target buffer for post-branch instructions based on past prediction accuracy's of branch predictions |
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2000-02-22 |
| 5953512 |
Microprocessor circuits, systems, and methods implementing a loop and/or stride predicting load target buffer |
Jonathan H. Shiell |
1999-09-14 |
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Multiple global pattern history tables for branch prediction in a microprocessor |
Jonathan H. Shiell |
1999-08-10 |
| 5909566 |
Microprocessor circuits, systems, and methods for speculatively executing an instruction using its most recently used data while concurrently prefetching data for the instruction |
Jonathan H. Shiell |
1999-06-01 |