Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Pratik A. Patel — 16 Patents

Intel: 14 patents #2,935 of 30,777Top 10%
University of California: 2 patents #4,561 of 18,278Top 25%
Portland, OR: #1,150 of 9,213 inventorsTop 15%
Oregon: #2,717 of 28,073 inventorsTop 10%
Overall (All Time): #284,196 of 4,157,543Top 7%
16 Patents All Time
Pratik A. Patel has been granted 16 US patents while listed as an inventor at Intel. The first was granted in 2013 and the most recent in September 2025. Pratik A. Patel ranks #284,196 of 4,157,543 US inventors in our database (top 6.8%). Patent records list Pratik A. Patel in Portland, OR, US.

Patents per Year

Patents granted per year, 2013 to 2025Bar chart with a peak of 3 patents in 2021.peak 32013: 1 patents20132015: 1 patents20152019: 1 patents20192020: 2 patents20202021: 3 patents20212022: 1 patents20222023: 2 patents20232024: 3 patents20242025: 2 patents2025

Issued Patents All Time

Showing 1–16 of 16 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12426299 Fin shaping and integrated circuit structures resulting therefrom Szuya S. Liao, Rahul Pandey, Rishabh Mehandru, Anupama Bowonder 2025-09-23
12224326 Contact architecture for capacitance reduction and satisfactory contact resistance Rishabh Mehandru, Ralph T. Troeger, Szuya S. Liao 2025-02-11
12027417 Source or drain structures with high germanium concentration capping layer Cory Bomberger, Suresh Vishwanath, Yulia Tolstova, Szuya S. Liao, Anand S. Murthy 2024-07-02 $27,114,000
11908940 Field effect transistor with a hybrid gate spacer including a low-k dielectric material Szuya S. Liao 2024-02-20 $26,968,000
11901457 Fin shaping and integrated circuit structures resulting therefrom Szuya S. Liao, Rahul Pandey, Rishabh Mehandru, Anupama Bowonder 2024-02-13 $18,546,000
11824097 Contact architecture for capacitance reduction and satisfactory contact resistance Rishabh Mehandru, Ralph T. Troeger, Szuya S. Liao 2023-11-21 $28,968,000
11664452 Diffused tip extension transistor Mark Liu, Jami A. Wiedemer, Paul Packan 2023-05-30 $16,378,000
11282930 Contact architecture for capacitance reduction and satisfactory contact resistance Rishabh Mehandru, Thomas T. TROEGER, Szuya S. Liao 2022-03-22 $16,833,000
11183592 Field effect transistor with a hybrid gate spacer including a low-k dielectric material Szuya S. Liao 2021-11-23 $33,627,000
11152461 Semiconductor layer between source/drain regions and gate spacers Rishabh Mehandru, Anupama Bowonder, Biswajeet Guha, Tahir Ghani, Stephen M. Cea +2 more 2021-10-19 $36,352,000
11101268 Transistors employing non-selective deposition of source/drain material Karthik Jambunathan, Scott Maddox, Ritesh Jhaveri, Szuya S. Liao, Anand S. Murthy +1 more 2021-08-24 $32,164,000
10872960 Contact architecture for capacitance reduction and satisfactory contact resistance Rishabh Mehandru, Thomas T. TROEGER, Szuya S. Liao 2020-12-22 $47,741,000
10872977 Diffused tip extension transistor Mark Liu, Jami A. Wiedemer, Paul Packan 2020-12-22 $47,741,000
10304956 Diffused tip extension transistor Mark Liu, Jami A. Wiedemer, Paul Packan 2019-05-28 $17,387,000
9117893 Tunneling transistor suitable for low voltage operation Chenming Hu, Anupama Bowonder, Daniel Chou, Prashant Majhi 2015-08-25
8384122 Tunneling transistor suitable for low voltage operation Chenming Hu, Anupama Bowonder, Daniel Chou, Prashant Majhi 2013-02-26