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USPTO Patent Rankings Data through Dec 31, 2025
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Paul Packan — 21 Patents

Intel: 21 patents #1,927 of 30,777Top 7%
Beaverton, OR: #278 of 3,140 inventorsTop 9%
Oregon: #2,048 of 28,073 inventorsTop 8%
Overall (All Time): #201,324 of 4,157,543Top 5%
21 Patents All Time
Paul Packan has been granted 21 US patents while listed as an inventor at Intel. The first was granted in 1998 and the most recent in May 2023. Paul Packan ranks #201,324 of 4,157,543 US inventors in our database (top 4.8%). Patent records list Paul Packan in Beaverton, OR, US.

Issued Patents All Time

Showing 1–21 of 21 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
11664452 Diffused tip extension transistor Pratik A. Patel, Mark Liu, Jami A. Wiedemer 2023-05-30 $16,378,000
11264517 CMOS varactor with increased tuning range Mohammed A. EL-TANANI, Jami A. Wiedemer, Andrey Mezhiba, Yonping Fan 2022-03-01 $16,941,000
10872977 Diffused tip extension transistor Pratik A. Patel, Mark Liu, Jami A. Wiedemer 2020-12-22 $47,741,000
10304956 Diffused tip extension transistor Pratik A. Patel, Mark Liu, Jami A. Wiedemer 2019-05-28 $17,387,000
9793373 Field effect transistor structure with abrupt source/drain junctions Anand S. Murthy, Robert S. Chau, Patrick Morrow, Chia-Hong Jan 2017-10-17 $9,876,000
9640634 Field effect transistor structure with abrupt source/drain junctions Anand S. Murthy, Robert S. Chau, Patrick Morrow, Chia-Hong Jan 2017-05-02 $12,076,000
7888710 CMOS fabrication process utilizing special transistor orientation Mark Armstrong, Gerhard Schrom, Sunit Tyagi, Kelin J. Kuhn, Scott Thompson 2011-02-15 $18,725,000
7682916 Field effect transistor structure with abrupt source/drain junctions Anand S. Murthy, Robert S. Chau, Patrick Morrow, Chia-Hong Jan 2010-03-23 $13,395,000
7436035 Method of fabricating a field effect transistor structure with abrupt source/drain junctions Anand S. Murthy, Robert S. Chau, Patrick Morrow, Chia-Hong Jan 2008-10-14 $13,671,000
7338873 Method of fabricating a field effect transistor structure with abrupt source/drain junctions Anand S. Murthy, Robert S. Chau, Patrick Morrow, Chia-Hong Jan 2008-03-04 $16,330,000
7312485 CMOS fabrication process utilizing special transistor orientation Mark Armstrong, Gerhard Schrom, Sunit Tyagi, Kelin J. Kuhn, Scott Thompson 2007-12-25
7226824 Nitrogen controlled growth of dislocation loop in stress enhanced transistor Cory E. Weber, Mark Armstrong, Harold W. Kennel, Tahir Ghani, Scott Thompson 2007-06-05 $17,840,000
7187057 Nitrogen controlled growth of dislocation loop in stress enhanced transistor Cory E. Weber, Mark Armstrong, Harold W. Kennel, Tahir Ghani, Scott Thompson 2007-03-06 $17,685,000
6887762 Method of fabricating a field effect transistor structure with abrupt source/drain junctions Anand S. Murthy, Robert S. Chau, Patrick Morrow, Chia-Hong Jan 2005-05-03 $20,343,000
6800887 Nitrogen controlled growth of dislocation loop in stress enhanced transistor Cory E. Weber, Mark Armstrong, Harold W. Kennel, Tahir Ghani, Scott Thompson 2004-10-05 $22,015,000
6326664 Transistor with ultra shallow tip and method of fabrication Robert S. Chau, Chan-Hong Chern, Chia-Hong Jan, Kevin R. Weldon, Leopoldo D. Yau 2001-12-04 $216,871,000
6198142 Transistor with minimal junction capacitance and method of fabrication Robert S. Chau, Chia-Hong Jan, Mitchell Taylor 2001-03-06 $156,843,000
6020244 Channel dopant implantation with automatic compensation for variations in critical dimension Scott Thompson, Tahir Ghani, Mark Stettler, Shahriar Ahmed, Mark Bohr 2000-02-01 $155,838,000
5976939 Low damage doping technique for self-aligned source and drain regions Scott Thompson, Mark Bohr 1999-11-02 $87,065,000
5908313 Method of forming a transistor Robert S. Chau, Chia-Hong Jan, Mitchell Taylor 1999-06-01 $142,810,000
5710450 Transistor with ultra shallow tip and method of fabrication Robert S. Chau, Chan-Hong Chern, Chia-Hong Jan, Kevin R. Weldon, Leopoldo D. Yau 1998-01-20 $163,168,000