Issued Patents All Time
Showing 26–50 of 62 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12046652 | Plug and recess process for dual metal gate on stacked nanoribbon devices | Nicole K. Thomas, Michael K. Harper, Marko Radosavljevic, Thoe Michaelos | 2024-07-23 |
| 12014959 | Integrated nanowire and nanoribbon patterning in transistor manufacture | Biswajeet Guha, Mark Armstrong, Tahir Ghani, William Hsu | 2024-06-18 |
| 12002810 | Gate-all-around integrated circuit structures having depopulated channel structures using bottom-up approach | Dax M. Crum, Biswajeet Guha, Tahir Ghani | 2024-06-04 |
| 11990472 | Fabrication of gate-all-around integrated circuit structures having pre-spacer deposition cut gates | Michael K. Harper, William Hsu, Biswajeet Guha, Tahir Ghani, Niels Zussblatt +6 more | 2024-05-21 |
| 11972979 | 1D vertical edge blocking (VEB) via and plug | Michael K. Harper, Suzanne S. Rich, Charles H. Wallace, Curtis W. Ward, Richard E. Schenker +4 more | 2024-04-30 |
| 11929396 | Cavity spacer for nanowire transistors | William Hsu, Biswajeet Guha, Souvik Chakrabarty, Jun Sung Kang, Bruce Beattie +1 more | 2024-03-12 |
| 11901458 | Dielectric isolation layer between a nanowire transistor and a substrate | Bruce Beattie, Biswajeet Guha, Jun Sung Kang, William Hsu | 2024-02-13 |
| 11862635 | Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions | Biswajeet Guha, Tahir Ghani, Swaminathan Sivakumar | 2024-01-02 |
| 11855223 | Self-aligned gate endcap (SAGE) architectures with gate-all-around devices | Biswajeet Guha, William Hsu, Dax M. Crum, Tahir Ghani | 2023-12-26 |
| 11749733 | FIN shaping using templates and integrated circuit structures resulting therefrom | Biswajeet Guha, Mark Armstrong, William Hsu, Tahir Ghani, Swaminathan Sivakumar | 2023-09-05 |
| 11742410 | Gate-all-around integrated circuit structures having oxide sub-fins | Biswajeet Guha, Tahir Ghani, Swaminathan Sivakumar | 2023-08-29 |
| 11721580 | 1D vertical edge blocking (VEB) via and plug | Michael K. Harper, Suzanne S. Rich, Charles H. Wallace, Curtis W. Ward, Richard E. Schenker +4 more | 2023-08-08 |
| 11715775 | Self-aligned gate endcap (SAGE) architectures with gate-all-around devices having epitaxial source or drain structures | Biswajeet Guha, Tahir Ghani, Swaminathan Sivakumar | 2023-08-01 |
| 11594448 | Vertical edge blocking (VEB) technique for increasing patterning process margin | Chul-Hyun Lim, Paul A. Nyhus, Elliot N. Tan, Charles H. Wallace | 2023-02-28 |
| 11594637 | Gate-all-around integrated circuit structures having fin stack isolation | Stephen D. Snyder, Biswajeet Guha, William Hsu, Urusa Alaan, Tahir Ghani +4 more | 2023-02-28 |
| 11581315 | Self-aligned gate edge trigate and finFET devices | Szuya S. Liao, Biswajeet Guha, Tahir Ghani, Christopher KENYON | 2023-02-14 |
| 11569370 | DEPOP using cyclic selective spacer etch | Vivek Thirtha, Shu Zhou, Nitesh Kumar, Biswajeet Guha, William Hsu +4 more | 2023-01-31 |
| 11569231 | Non-planar transistors with channel regions having varying widths | Stephen D. Snyder, Richard E. Schenker, Michael K. Harper, Sam Sivakumar, Urusa Alaan +2 more | 2023-01-31 |
| 11538937 | Fin trim plug structures having an oxidation catalyst layer surrounded by a recessed dielectric material | Nick Lindert, Biswajeet Guha, Swaminathan Sivakumar, Tahir Ghani | 2022-12-27 |
| 11527433 | Via and plug architectures for integrated circuit interconnects and methods of manufacture | Charles H. Wallace, Paul A. Nyhus | 2022-12-13 |
| 11404578 | Dielectric isolation layer between a nanowire transistor and a substrate | Bruce Beattie, Biswajeet Guha, Jun Sung Kang, William Hsu | 2022-08-02 |
| 11398474 | Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions | Biswajeet Guha, Tahir Ghani, Swaminathan Sivakumar | 2022-07-26 |
| 11355608 | Self-aligned gate endcap (SAGE) architectures with gate-all-around devices having epitaxial source or drain structures | Biswajeet Guha, Tahir Ghani, Swaminathan Sivakumar | 2022-06-07 |
| 11342411 | Cavity spacer for nanowire transistors | William Hsu, Biswajeet Guha, Souvik Chakrabarty, Jun Sung Kang, Bruce Beattie +1 more | 2022-05-24 |
| 11302790 | Fin shaping using templates and integrated circuit structures resulting therefrom | Biswajeet Guha, Mark Armstrong, William Hsu, Tahir Ghani, Swaminathan Sivakumar | 2022-04-12 |