Issued Patents All Time
Showing 25 most recent of 40 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11933844 | Path based controls for ATE mode testing of multicell memory circuit | Wilson Pradeep | 2024-03-19 |
| 11921159 | Compressed scan chain diagnosis by internal chain observation, processes, circuits, devices and systems | Rubin Ajit Parekhji, Arvind Jain, Sundarrajan Subramanian | 2024-03-05 |
| 11879940 | Dynamic generation of ATPG mode signals for testing multipath memory circuit | Wilson Pradeep | 2024-01-23 |
| 11852683 | Scan chain self-testing of lockstep cores on reset | Nikita Naresh | 2023-12-26 |
| 11821945 | Full pad coverage boundary scan | Rajesh Mittal, Rajat Mehrotra | 2023-11-21 |
| 11768726 | Delay fault testing of pseudo static controls | Aravinda Acharya, Wilson Pradeep | 2023-09-26 |
| 11709203 | Transition fault testing of functionally asynchronous paths in an integrated circuit | Sundarrajan Rangachari, Prashanth Saraf | 2023-07-25 |
| 11592483 | Compressed scan chain diagnosis by internal chain observation, processes, circuits, devices and systems | Rubin Ajit Parekhji, Arvind Jain, Sundarrajan Subramanian | 2023-02-28 |
| 11555853 | Scan chain self-testing of lockstep cores on reset | Nikita Naresh | 2023-01-17 |
| 11519964 | Phase controlled codec block scan of a partitioned circuit device | Wilson Pradeep | 2022-12-06 |
| 11521698 | Testing read-only memory using memory built-in self-test controller | Nikita Naresh, Prathyusha Teja Inuganti, Rakesh Channabasappa Yaraduyathinahalli, Aravinda Acharya, Jasbir Singh +1 more | 2022-12-06 |
| 11300615 | Transistion fault testing of funtionally asynchronous paths in an integrated circuit | Sundarrajan Rangachari, Prashanth Saraf | 2022-04-12 |
| 11209481 | Multiple input signature register analysis for digital circuitry | Naman Maheshwari, Wilson Pradeep | 2021-12-28 |
| 11194645 | Delay fault testing of pseudo static controls | Aravinda Acharya, Wilson Pradeep | 2021-12-07 |
| 11194944 | False path timing exception handler circuit | Wilson Pradeep, Saket Jalan | 2021-12-07 |
| 11119152 | Functional circuitry, decompressor circuitry, scan circuitry, masking circuitry, qualification circuitry | Rubin Ajit Parekhji, Arvind Jain, Sundarrajan Subramanian | 2021-09-14 |
| 11073557 | Phase controlled codec block scan of a partitioned circuit device | Wilson Pradeep | 2021-07-27 |
| 11073553 | Dynamic generation of ATPG mode signals for testing multipath memory circuit | Wilson Pradeep | 2021-07-27 |
| 11047910 | Path based controls for ATE mode testing of multicell memory circuit | Wilson Pradeep | 2021-06-29 |
| 10983161 | Full pad coverage boundary scan | Rajesh Mittal, Rajat Mehrotra | 2021-04-20 |
| 10866280 | Scan chain self-testing of lockstep cores on reset | Nikita Naresh | 2020-12-15 |
| 10818374 | Testing read-only memory using memory built-in self-test controller | Nikita Naresh, Prathyusha Teja Inuganti, Rakesh Channabasappa Yaraduyathinahalli, Aravinda Acharya, Jasbir Singh +1 more | 2020-10-27 |
| 10776546 | False path timing exception handler circuit | Wilson Pradeep, Saket Jalan | 2020-09-15 |
| 10591540 | Compressed scan chains with three input mask gates and registers | Rubin Ajit Parekhji, Arvind Jain, Sundarrajan Subramanian | 2020-03-17 |
| 10579454 | Delay fault testing of pseudo static controls | Aravinda Acharya, Wilson Pradeep | 2020-03-03 |