Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11740968 | Error correction hardware with fault detection | Indu Prathapan, Abhishek Ganapati Karkisaval | 2023-08-29 |
| 11631454 | Methods and apparatus for reduced area control register circuit | Sudesh Chandra Srivastava, Mohammed Nabeel | 2023-04-18 |
| 11538069 | Presenting content items associated with dynamically-created advertisements to users of a social networking system | Scott Shapiro, Shreehari Manikarnika, Brian M. Wrightson, Gang Wu | 2022-12-27 |
| 11372715 | Error correction hardware with fault detection | Indu Prathapan, Abhishek Ganapati Karkisaval | 2022-06-28 |
| 11320488 | Self test for safety logic | Sundarrajan Rangachari | 2022-05-03 |
| 11194944 | False path timing exception handler circuit | Wilson Pradeep, Prakash Narayanan | 2021-12-07 |
| 10935602 | Self test for safety logic | Sundarrajan Rangachari | 2021-03-02 |
| 10838808 | Error-correcting code memory | Indu Prathapan, Prashanth Saraf, Desmond Pravin Martin Fernandes | 2020-11-17 |
| 10776546 | False path timing exception handler circuit | Wilson Pradeep, Prakash Narayanan | 2020-09-15 |
| 10599514 | Error correction hardware with fault detection | Indu Prathapan, Abishek Ganapati Karkisaval | 2020-03-24 |
| 10559351 | Methods and apparatus for reduced area control register circuit | Sudesh Chandra Srivastava, Mohammed Nabeel | 2020-02-11 |
| 10445785 | Presenting content items associated with dynamically-created advertisements to users of a social networking system | Scott Shapiro, Shreehari Manikarnika, Brian M. Wrightson, Gang Wu | 2019-10-15 |
| 10372531 | Error-correcting code memory | Indu Prathapan, Prashanth Saraf, Desmond Pravin Martin Fernandes | 2019-08-06 |
| 10331826 | False path timing exception handler circuit | Wilson Pradeep, Prakash Narayanan | 2019-06-25 |
| 9964597 | Self test for safety logic | Sundarrajan Rangachari | 2018-05-08 |
| 9904595 | Error correction hardware with fault detection | Indu Prathapan, Abhishek Ganapati Karkisaval | 2018-02-27 |
| 9602107 | Reset selection cell to mitigate initialization time | Abhishek Ganapati Karkisaval | 2017-03-21 |
| 9361027 | System and method for fast modification of register content | Rakesh Channabasappa Yaraduyathinahalli | 2016-06-07 |
| 9287876 | Fully automated. high throughput, configurable digital design internal functional node probing mechanism and method | Mohammed Nabeel | 2016-03-15 |
| 8971455 | Near-integer channel spur mitigation in a phase-locked loop | Raghu Ganesan | 2015-03-03 |
| 7817747 | Precise delay alignment between amplitude and phase/frequency modulation paths in a digital polar transmitter | Khurram Waheed, Jayawardan Janardhanan, Sameh S. Rezeq, Robert Bogdan Staszewski | 2010-10-19 |
| 7548179 | MASH sigma delta modulator | — | 2009-06-16 |