Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12216160 | Clock shaper circuit for transition fault testing | Sriraj Chellappan, Shruti Gupta | 2025-02-04 |
| 11933844 | Path based controls for ATE mode testing of multicell memory circuit | Prakash Narayanan | 2024-03-19 |
| 11879940 | Dynamic generation of ATPG mode signals for testing multipath memory circuit | Prakash Narayanan | 2024-01-23 |
| 11768726 | Delay fault testing of pseudo static controls | Aravinda Acharya, Prakash Narayanan | 2023-09-26 |
| 11680984 | Control data registers for scan testing | Aravinda Acharya, Nikita Naresh | 2023-06-20 |
| 11604221 | Clock shaper circuit for transition fault testing | Sriraj Chellappan, Shruti Gupta | 2023-03-14 |
| 11519964 | Phase controlled codec block scan of a partitioned circuit device | Prakash Narayanan | 2022-12-06 |
| 11333707 | Testing of integrated circuits during at-speed mode of operation | Khushboo Agarwal, Sanjay Krishna Hulical Vijayaraghavachar, Raashid Moin Shaikh, Srivaths Ravi, Rajesh Tiwari | 2022-05-17 |
| 11209481 | Multiple input signature register analysis for digital circuitry | Naman Maheshwari, Prakash Narayanan | 2021-12-28 |
| 11194645 | Delay fault testing of pseudo static controls | Aravinda Acharya, Prakash Narayanan | 2021-12-07 |
| 11194944 | False path timing exception handler circuit | Prakash Narayanan, Saket Jalan | 2021-12-07 |
| 11073553 | Dynamic generation of ATPG mode signals for testing multipath memory circuit | Prakash Narayanan | 2021-07-27 |
| 11073557 | Phase controlled codec block scan of a partitioned circuit device | Prakash Narayanan | 2021-07-27 |
| 11047910 | Path based controls for ATE mode testing of multicell memory circuit | Prakash Narayanan | 2021-06-29 |
| 10776546 | False path timing exception handler circuit | Prakash Narayanan, Saket Jalan | 2020-09-15 |
| 10579454 | Delay fault testing of pseudo static controls | Aravinda Acharya, Prakash Narayanan | 2020-03-03 |
| 10473717 | Methods and apparatus for test insertion points | — | 2019-11-12 |
| 10331826 | False path timing exception handler circuit | Prakash Narayanan, Saket Jalan | 2019-06-25 |
| 10184980 | Multiple input signature register analysis for digital circuitry | Naman Maheshwari, Prakash Narayanan | 2019-01-22 |
| 9535123 | Frequency scaled segmented scan chain for integrated circuits | Rajesh Mittal, Vivek Singhal | 2017-01-03 |