Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12142337 | System and method for parallel memory test | Nitesh Mishra | 2024-11-12 |
| 11852683 | Scan chain self-testing of lockstep cores on reset | Prakash Narayanan | 2023-12-26 |
| 11776656 | System and method for parallel memory test | Nitesh Mishra | 2023-10-03 |
| 11715544 | System and method for low power memory test | Nitesh Mishra | 2023-08-01 |
| 11680984 | Control data registers for scan testing | Wilson Pradeep, Aravinda Acharya | 2023-06-20 |
| 11555853 | Scan chain self-testing of lockstep cores on reset | Prakash Narayanan | 2023-01-17 |
| 11521698 | Testing read-only memory using memory built-in self-test controller | Prakash Narayanan, Prathyusha Teja Inuganti, Rakesh Channabasappa Yaraduyathinahalli, Aravinda Acharya, Jasbir Singh +1 more | 2022-12-06 |
| 10866280 | Scan chain self-testing of lockstep cores on reset | Prakash Narayanan | 2020-12-15 |
| 10818374 | Testing read-only memory using memory built-in self-test controller | Prakash Narayanan, Prathyusha Teja Inuganti, Rakesh Channabasappa Yaraduyathinahalli, Aravinda Acharya, Jasbir Singh +1 more | 2020-10-27 |
| 10460821 | Area efficient parallel test data path for embedded memories | Prakash Narayanan, Vaskar Sarkar, Rajat Mehrotra | 2019-10-29 |
| 9899103 | Area efficient parallel test data path for embedded memories | Prakash Narayanan, Vaskar Sarkar, Rajat Mehrotra | 2018-02-20 |